Hybrid super/subthreshold design of a low power scalable-throughput FFT architecture

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 5409 LNCS, Issue , 2009, Pages 278-292

  Henry, Michael B ^a   Nazhandali, Leyla ^a  

^a VIRGINIA POLYTECHNIC INSTITUTE AND STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BATTERY POWER; HIGH THROUGHPUTS; LOW-POWER; MEMORY BANKS; PARALLEL DESIGNS; PARALLEL IMPLEMENTATIONS; PARALLEL PROCESSING; POWER CONSUMPTION; PROCESSING ELEMENTS; SCALING METHODS; SUB THRESHOLDS; SUPPLY VOLTAGES; VOLTAGE-SCALING;

DESIGN; ELECTRIC POWER UTILIZATION; FAST FOURIER TRANSFORMS; FOURIER TRANSFORMS; HIGH PERFORMANCE LIQUID CHROMATOGRAPHY; PROGRAM COMPILERS; TELECOMMUNICATION EQUIPMENT; TRANSISTORS;

THROUGHPUT;

EID: 59049089426     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-92990-1_21     Document Type: Conference Paper

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