Architecture and physical implementation of a third generation 65 nm, 16 Core, 32 thread chip-multithreading SPARC processor

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 1, 2009, Pages 7-17

  Konstadinidis, Georgios K ^a   Tremblay, Marc ^a   Chaudhry, Shailender ^a   Rashid, Mamun ^a   Lai, Peter F ^a   Otaguro, Yukio ^a   Orginos, Yannis ^a   Parampalli, Sudhendra ^a   Steigerwald, Mark ^a   Gundala, Shriram ^a   Pyapali, Rambabu ^a   Rarick, Leonard D ^a   Elkin, Ilyas ^a   Ge, Yuefei ^a   Parulkar, Ishwar ^a  

^a SUN MICROSYSTEMS   (United States)

Author keywords

Arrays; Chip multi threading (CMT); Clocking; Computer architecture; Execute ahead; Hardware scout; Microprocessor; Multi core; Multi threaded; Power management; Register files; SerDes; SPARC architecture; Transactional memory

Indexed keywords

ARCHITECTURE; COMPUTER ARCHITECTURE; COMPUTERS; ELECTRIC POWER MEASUREMENT; ENERGY MANAGEMENT; MICROPROCESSOR CHIPS; MULTITASKING; STORAGE ALLOCATION (COMPUTER); TIMING JITTER;

ARRAYS; CHIP MULTI-THREADING (CMT); CLOCKING; EXECUTE AHEAD; MICROPROCESSOR; MULTI-CORE; MULTI-THREADED; POWER MANAGEMENT; REGISTER FILES; SERDES; SPARC ARCHITECTURE; TRANSACTIONAL MEMORY;

COMPUTER HARDWARE;

EID: 58149265194     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2007144     Document Type: Conference Paper

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