Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Volumn , Issue , 2007, Pages 607-610

  Zou, Jun ^a,b   Graeb, Helmut ^a   Mueller, Daniel ^a   Schlichtmann, Ulf ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b QIMONDA DRESDEN GMBH AND CO OHG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG INTEGRATED CIRCUITS; COMPOSITE STRUCTURES; INTEGRATED CIRCUITS; OPERATIONAL AMPLIFIERS; SPACE RESEARCH;

FEASIBLE REGIONS; OPTIMIZATION METHOD; PARETO-OPTIMAL FRONT; PERFORMANCE CAPABILITY; PERFORMANCE SPACE EXPLORATION; SIGMA DELTA MODULATOR; SWITCHED CAPACITOR; WORST-CASE ANALYSIS;

PARETO PRINCIPLE;

EID: 58149125885     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405805     Document Type: Conference Paper

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