A multilayer process for fine-pitch assemblies on molded interconnect devices (MIDs)

Proceedings - 2008 2nd Electronics Systemintegration Technology Conference, ESTC

Volumn , Issue , 2008, Pages 663-668

  Leneke, Thomas ^a   Hirsch, Soeren ^a   Schmidt, Bertram ^a  

^a OTTO VON GUERICKE UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; ELECTRIC CONDUCTIVITY; ELECTRIC CONNECTORS; ELECTRONICS PACKAGING; MULTILAYERS; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR MATERIALS;

BARE DIES; ELECTRICAL CONNECTIONS; HIGH DENSITIES; HIGH POTENTIALS; I/O COUNTS; MECHANICAL BEHAVIORS; MECHANICAL SUPPORTS; METALLIZATION PROCESSES; MOLDED INTERCONNECT DEVICES; MULTILAYER PROCESSES; MULTILAYER TECHNOLOGIES; OVERALL SYSTEMS; SEMI-CONDUCTORS; SEMICONDUCTOR PACKAGES; SILICON DEVICES; SMART PACKAGES; TECHNOLOGICAL APPLICATIONS; THERMAL MANAGEMENTS;

ELECTRONIC EQUIPMENT MANUFACTURE;

EID: 58149085206     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESTC.2008.4684430     Document Type: Conference Paper

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