A general model of concurrency and its implementation as many-core dynamic RISC processors

Proceedings - 2008 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2008

Volumn , Issue , 2008, Pages 1-9

  Bernard, T ^a   Bousias, K ^a   Guang, L ^a   Jesshope, C R ^a   Lankamp, M ^a   Van Tol, M W ^a   Zhang, L ^a  

^a UNIVERSITY OF AMSTERDAM   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE; BINARY CODES; EMBEDDED SYSTEMS; ENERGY EFFICIENCY; PROGRAM COMPILERS; REDUCED INSTRUCTION SET COMPUTING;

ASYNCHRONOUS OPERATIONS; CHIP MULTIPROCESSORS; CONCURRENT EXECUTION MODELS; DYNAMIC DISTRIBUTIONS; GENERAL MODELS; LOOP STRUCTURES; MANY CORES; MUTUAL EXCLUSIONS; ORDERS OF MAGNITUDES; PARAMETERISATION; RISC PROCESSORS; SEQUENTIAL CODES; SIMULATION AND ANALYSES; SPEED-UP;

COMPUTER ARCHITECTURE;

EID: 58049192632     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSAMOS.2008.4664840     Document Type: Conference Paper

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