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Volumn , Issue , 2008, Pages 209-212

Sensitivity computation of interconnect capacitances with respect to geometric parameters

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ELECTRONICS PACKAGING; NUMERICAL ANALYSIS; SENSITIVITY ANALYSIS;

EID: 58049114599     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEP.2008.4675916     Document Type: Conference Paper
Times cited : (6)

References (7)
  • 1
    • 51549110620 scopus 로고    scopus 로고
    • Efficient algorithm for the computation of on-chip capacitance sensitivities with respect to a large set of parameters
    • T. El-Moselhy, I. M. Elfadel, and D. Widiger, "Efficient algorithm for the computation of on-chip capacitance sensitivities with respect to a large set of parameters," in Proc. 45th ACM/IEEE Design Automation Conference DAC 2008, pp. 906-911, 2008.
    • (2008) Proc. 45th ACM/IEEE Design Automation Conference DAC , pp. 906-911
    • El-Moselhy, T.1    Elfadel, I.M.2    Widiger, D.3
  • 2
    • 2942576140 scopus 로고    scopus 로고
    • Rapid method to account for process variation in full-chip capacitance extraction
    • A. Labun, "Rapid method to account for process variation in full-chip capacitance extraction," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst, vol. 23, no. 6, pp. 941-951, 2004.
    • (2004) IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst , vol.23 , Issue.6 , pp. 941-951
    • Labun, A.1
  • 4
    • 34548346740 scopus 로고    scopus 로고
    • R Ghanta and S. Vrudhula, Variational interconnect delay metrics for statistical timing analysis, in Proc. 7th International Symposium on Quality Electronic Design ISOED '06, pp. 6 pp.- 2006.
    • R Ghanta and S. Vrudhula, "Variational interconnect delay metrics for statistical timing analysis," in Proc. 7th International Symposium on Quality Electronic Design ISOED '06, pp. 6 pp.- 2006.
  • 5
    • 51849140175 scopus 로고    scopus 로고
    • Y. Bi, N. van der Meijs, and D. loan, Capacitance sensitivity calculation for interconnects by adjoint field technique, in 12th IEEE Workshop on Signal Propagation on Interconnects, 2008.
    • Y. Bi, N. van der Meijs, and D. loan, "Capacitance sensitivity calculation for interconnects by adjoint field technique," in 12th IEEE Workshop on Signal Propagation on Interconnects, 2008.
  • 6
    • 0016655298 scopus 로고
    • Capacitance models for integrated circuit metallization wires
    • A. Ruehli and P. Brennan, "Capacitance models for integrated circuit metallization wires," IEEE J. Solid-State Circuits, vol. 10, no. 6, pp. 530-536,1975.
    • (1975) IEEE J. Solid-State Circuits , vol.10 , Issue.6 , pp. 530-536
    • Ruehli, A.1    Brennan, P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.