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Volumn , Issue , 2008, Pages 906-911

Efficient algorithm for the computation of on-chip capacitance sensitivities with respect to a large set of parameters

Author keywords

Adjoint method; Capacitance extraction; Sensitivity analysis

Indexed keywords

ADJOINT METHOD; CAPACITANCE EXTRACTION; DESIGN AUTOMATION CONFERENCE; SENSITIVITY ANALYSIS;

EID: 51549110620     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555949     Document Type: Conference Paper
Times cited : (8)

References (10)
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    • Iverson, R.B.1    Le Coz, Y.L.2
  • 2
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    • Sylvester, D.1    Hu, D.2
  • 3
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    • The Direct Solution of the Discrete Poisson Equation on a Rectangle
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    • (1970) SIAM Review , vol.12 , pp. 248-263
    • Dorr, F.1
  • 4
    • 0000208736 scopus 로고
    • Generalized Adjoint Network and Network Sensitivities
    • S. W. Director and R. A. Rohrer, "Generalized Adjoint Network and Network Sensitivities" IEEE Trans. Circuit Theory, vol. CT-16, pp. 318-323, 1969.
    • (1969) IEEE Trans. Circuit Theory , vol.CT-16 , pp. 318-323
    • Director, S.W.1    Rohrer, R.A.2
  • 5
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    • Network Sensitivity and Noise Analysis Simplified
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  • 6
    • 0001645732 scopus 로고    scopus 로고
    • JiffyTune: Circuit Optimization Using Time-Domain Sensitivities
    • A. R. Conn et. al., "JiffyTune: Circuit Optimization Using Time-Domain Sensitivities" IEEE Trans. CAD, vol. 17, pp. 1292-1309, 1998.
    • (1998) IEEE Trans. CAD , vol.17 , pp. 1292-1309
    • Conn, A.R.1    et., al.2
  • 7
    • 0030647090 scopus 로고    scopus 로고
    • Fast Algorithms for Computing Electrostatic Geometric Sensitivities
    • J. Wang and J. White., "Fast Algorithms for Computing Electrostatic Geometric Sensitivities" SISPAD'97, pp. 121-123, 1997.
    • (1997) SISPAD'97 , pp. 121-123
    • Wang, J.1    White, J.2
  • 8
    • 0022603501 scopus 로고
    • A Methodology for Worst-Case Analysis of Integrated Circuits
    • S. Nassif, A. J. Strojwas, S. W. Director, "A Methodology for Worst-Case Analysis of Integrated Circuits" IEEE Tran. CAD, Vol. 5, pp. 104-113, 1986.
    • (1986) IEEE Tran. CAD , vol.5 , pp. 104-113
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  • 9
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    • Fast Generation of Statistically-based Worst-Case Modeling of On-Chip Interconnect
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  • 10
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    • T. A. El-Moselhy and I. M. Elfadel, Method And System For The Calculation Of The Sensitivities Of An Electrical Parameter Of An Integrated Circuit, IBM Docket Number YOR9-2007-0625-US1. US Patent pending
    • T. A. El-Moselhy and I. M. Elfadel, "Method And System For The Calculation Of The Sensitivities Of An Electrical Parameter Of An Integrated Circuit," IBM Docket Number YOR9-2007-0625-US1. US Patent pending.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.