Hierarchical and adaptive finite-element reduction-recovery method for large-scale power and signal integrity analysis of high-speed IC and packaging structures

Electrical Performance of Electronic Packaging, EPEP

Volumn , Issue , 2008, Pages 127-130

  Gan, Houle ^a   He, Qing ^a   Jiao, Dan ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

Electromagnetic simulation; Large scale; On chip; Power and signal integrity; Transient analysis

Indexed keywords

ACTIVE LAYERS; ADAPTIVE REDUCTIONS; AND RECOVERIES; ELECTROMAGNETIC SIMULATION; ELEMENT REDUCTIONS; LARGE-SCALE; MATRIX FACTORIZATIONS; MATRIX REDUCTIONS; MEMORY OVERHEADS; MULTILAYER SYSTEMS; ON-CHIP; ORIGINAL PROBLEMS; PACKAGING STRUCTURES; POWER AND SIGNAL INTEGRITY; RECOVERY SCHEMES; TIME STEPS;

CHIP SCALE PACKAGES; DATA STORAGE EQUIPMENT; ELECTRONIC EQUIPMENT MANUFACTURE; ELECTRONICS PACKAGING; QUALITY ASSURANCE; REAL TIME SYSTEMS; SIGNAL PROCESSING; TRANSIENT ANALYSIS;

FINITE ELEMENT METHOD;

EID: 58049086657     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEP.2008.4675894     Document Type: Conference Paper

References (6)

1. H. Gan and D. Jiao, "A Fast and High-Capacity Electromagnetic Solution for High-Speed IC Design," ICCAD, pp. 1-6, 2007.
2. H. Gan and D. Jiao, "A Time-Domain Layered Finite Element Reduction Recovery (LAFE-RR) Method for High-Frequency VLSI Design," IEEE Trans. Antennas Propagat., vol. 55, no. 12, pp. 3620-3629, Dec. 2007
3. UMFPACK,http://www.cise.ufl.edu/research/sparse/umfpack/.
4. J. M. Jin, The Finite Element Method in Electromagnetics. New York: John Wiley & Sons, 2nd edition, 2002.
5. H. Gan and D. Jiao, "A Recovery Algorithm of Linear Complexity in the Time-Domain Layered Finite Element Reduction Recovery (LAFERR) Method for Large-Scale Electromagnetic Analysis of High-Speed ICs," accepted for publication, IEEE Trans, on Advanced Packaging, 2007.
6. M. J. Kobrinsky, S. Chakravarty, D. Jiao, M. Harmes, S. List, and M. Mazumder, "Experimental validation of crosstalk simulations for on-chip interconnects at high frequencies using S-parameters," EPEP 2003, pp. 329-332.