A recovery algorithm of linear complexity in the time-domain layered finite element reduction recovery (LAFE-RR) method for large scale electromagnetic analysis of high-speed ICs

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn , Issue , 2007, Pages 287-290

  Gan, Houle ^a   Jiao, Dan ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

Electromagnetic simulation; Large scale; On chip; Time domain

Indexed keywords

DIRECT SOLUTIONS; DO-MAINS; EFFICIENT ALGORITHMS; ELECTROMAGNETIC ANALYSIS; ELECTROMAGNETIC SIMULATION; LARGE-SCALE; LAYERED FINITE ELEMENTS; LINEAR COMPLEXITIES; MATRIX FACTORIZATIONS; MATRIX SOLUTIONS; MEMORY CONSUMPTIONS; MULTILAYER CIRCUITS; ON-CHIP; ORIGINAL PROBLEMS; ORIGINAL SYSTEMS; RECOVERY ALGORITHMS; RUN TIMES; SINGLE LAYERS; SYSTEM MATRIXES; TIME DOMAIN;

CHIP SCALE PACKAGES; ELECTROMAGNETISM; ELECTRONIC EQUIPMENT MANUFACTURE; ELECTRONICS PACKAGING; FINITE ELEMENT METHOD; LANTHANUM ALLOYS; MAGNETIC MATERIALS; METHOD OF MOMENTS; REAL TIME SYSTEMS;

TIME DOMAIN ANALYSIS;

EID: 47949121701     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEP.2007.4387183     Document Type: Conference Paper

References (6)

1. H. Gan and D. Jiao, "A Time-Domain Layered Finite Element Reduction Recovery Method (LAFE-RR) for High-Frequency VLSI Design," IEEE International Symp. on Antennas and Propagat., June 2007.
2. H. Gan and D. Jiao, "A Fast and High-Capacity Electromagnetic Solution for High-Speed IC Design," ICCAD, accepted for publication, 2007.
3. UMFPACK,http://www.cise.ufl.edu/research/sparse/umfpack/.
4. D. Jiao and J. M. Jin, "Finite element analysis in time domain," in The Finite Element Method in Electromagnetics, New York: John Wiley & Sons, 2002, pp. 529-584.
5. G. Meurant, "A review on the inverse of symmetric tridiagonal and block tridiagonal matrices," SIAM J. on Matrix Analysis and Applications, 13(3):707-728, July 1992.
6. M. J. Kobrinsky, S. Chakravarty, D. Jiao, M. Harmes, S. List, and M. Mazumder, "Experimental validation of crosstalk simulations for on-chip interconnects at high frequencies using S-parameters", EPEP 2003, pp. 329-332.