High throughput hardware architecture for (1440,1344) low-density parity-check code utilizing quasi-cyclic structure

2008 5th International Symposium on Turbo Codes and Related Topics, TURBOCODING

Volumn , Issue , 2008, Pages 78-83

  Yamagishi, Hiroyuki ^a   Noda, Makoto ^a  

^a SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE; BIT ERROR RATE; CHANNEL CODING; CMOS INTEGRATED CIRCUITS; COMMUNICATION CHANNELS (INFORMATION THEORY); DECODING; MESSAGE PASSING; THROUGHPUT; TRANSCEIVERS; TURBO CODES;

65NM CMOS TECHNOLOGIES; BIT-ERROR RATES; DECODER ARCHITECTURES; ENCODING METHODS; GATE COUNTS; HARDWARE ARCHITECTURES; HIGH THROUGHPUTS; LDPC CODES; LOW-DENSITY PARITY-CHECK CODES; MEMORY ACCESSES; POWER CONSUMPTIONS; PROPOSED ARCHITECTURES; QUASI-CYCLIC;

CODES (SYMBOLS);

EID: 57849162042     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TURBOCODING.2008.4658676     Document Type: Conference Paper

References (13)

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