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Volumn 6521, Issue , 2007, Pages

Patterning effect and correlated electrical model of post-OPC MOSFET devices

Author keywords

ADI; CD; DFM; DRC; MOSFET

Indexed keywords

COMPUTER SIMULATION; ETCHING; INTEGRATED CIRCUITS; MOSFET DEVICES; PATTERN RECOGNITION; SPICE;

EID: 35148860623     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.717254     Document Type: Conference Paper
Times cited : (7)

References (6)
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    • (1983) IEEE Transactions on Electron Devices , vol.ED-30 , pp. 1251
    • Liu, A.1    Lin, B.J.2
  • 2
    • 24944578595 scopus 로고
    • Proximity Effects in Submicron Optical Lithography
    • P. Chien and M. Chen, "Proximity Effects in Submicron Optical Lithography", Proc. SPIE, 772, 35(1987).
    • (1987) Proc. SPIE , vol.772 , pp. 35
    • Chien, P.1    Chen, M.2
  • 3
    • 85076464313 scopus 로고
    • Fast Proximity Correction with Zone Sampling
    • J.P. Stirniman and M.L. Rieger, "Fast Proximity Correction with Zone Sampling", Proc. SPIE, 2197, 294(1994).
    • (1994) Proc. SPIE , vol.2197 , pp. 294
    • Stirniman, J.P.1    Rieger, M.L.2
  • 4
    • 4344591506 scopus 로고    scopus 로고
    • Shiying Xiong, Bokor J, Qi Xiang, Fisher P, Dudley I, Paula Rao, Haihong Wang, En B. Is gate line edge roughness a first-order issue in affecting the performance of deep sub-micro bulk MOSFET devices? IEEE Transactions on Semiconductor Manufacturing, 17, no.3, Aug. 2004, pp.357-61.
    • Shiying Xiong, Bokor J, Qi Xiang, Fisher P, Dudley I, Paula Rao, Haihong Wang, En B. "Is gate line edge roughness a first-order issue in affecting the performance of deep sub-micro bulk MOSFET devices?" IEEE Transactions on Semiconductor Manufacturing, vol.17, no.3, Aug. 2004, pp.357-61.
  • 5
    • 33745608353 scopus 로고    scopus 로고
    • From Poly Line to Transistor: Building BSIM Models for Non-Rectangular Transistors
    • 61560P
    • W. J. Poppe, L. Capodieci, J. Wu, and A. Neureuther, "From Poly Line to Transistor: Building BSIM Models for Non-Rectangular Transistors", Proc. of SPIE Vol. 6156, 61560P, (2006).
    • (2006) Proc. of SPIE , vol.6156
    • Poppe, W.J.1    Capodieci, L.2    Wu, J.3    Neureuther, A.4
  • 6
    • 33748065992 scopus 로고    scopus 로고
    • Optimization of layout design and OPC by using estimation of transistor properties
    • 62830P
    • K. Koike, K. Nakayama, K. Ogawa, and H. Ohnuma, "Optimization of layout design and OPC by using estimation of transistor properties", Proc. of SPIE Vol. 6283, 62830P, (2006).
    • (2006) Proc. of SPIE , vol.6283
    • Koike, K.1    Nakayama, K.2    Ogawa, K.3    Ohnuma, H.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.