Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2008, Pages 415-418

  Arslan, Umut ^a   McCartney, Mark P ^a   Bhargava, Mudit ^a   Li, Xin ^a   Mai, Ken ^a   Pileggi, Lawrence T ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT LINES; CONFIGURABLE; EXPONENTIAL REDUCTIONS; MEASURED RESULTS; SILICON TESTS; STATISTICAL SELECTIONS; TEST CHIPS; TIMING VARIATIONS;

AUTOMOBILE DRIVERS; INTEGRATED CIRCUITS; STATIC RANDOM ACCESS STORAGE;

TIME MEASUREMENT;

EID: 57849143871     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2008.4672108     Document Type: Conference Paper

References (5)

1. B. Amrutur and M. Horowitz, "A replica technique for wordline and sense control in. low-power SRAM's," JSSC, Aug. 1998.
2. R. Heald and P. Wang, "Variability in sub-100nm. SRAM designs," ICCAD, Nov. 2004.
3. K. Osada, et al., "Universal-Vdd 0.65-2.0-V 32-k.B cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell," JSSC, Nov. 2001.
4. R.D. Adams, High performance memory testing, Kluwer Academic Publishers, 2003.
5. R. Ho, et al., "Applications of on-chip samplers for test and measurement of integrated circuits," Symposium on VLSI Circuits, 1998.