Integrating III-V on silicon for future nanoelectronics

2008 IEEE CSIC Symposium: GaAs ICs Celebrate 30 Years in Monterey, Technical Digest 2008

Volumn , Issue , 2008, Pages

  Hudait, Mantu K ^a   Chau, Robert ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 57849111473     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CSICS.2008.8     Document Type: Conference Paper

References (8)

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2. M. Bohr, R. Chau, T. Ghani and K. Mistry, "The High-k Solution," IEEE Spectrum, Oct 2007, pp. 29-35.
3. R. Chau, B. Doyle, S. Datta, J. Kavalieros and K. Zhang, "Integrated nanoelectronics for the future," Nature Materials, Vol. 6, Nov 2007, pp. 810-812.
4. T. Ashley, L. Buckle, S. Datta, M.T. Emeny, D.G Hayes, K.P. Hilton, R. Jefferies, T. Martin, T.J. Philips, D.J. Wallis, P.J. Wilding and R. Chau, "Heterogeneous InSb quantum well transistors on silicon for ultra-high speed, low power
5. logic applications," Electronics Letters, Vol. 43, No. 14, July 2007.
6. 0.3As HEMTs for Logic," International Electron Devices Meeting (1EDM) Technical Digest, 2006, pp. 837-840.
7. R. Chau, "III-V on Silicon for Future High Speed and Ultra-low Power Digital Applications: Challenges and Opportunities," CS Mantech Conference 2008, Digest of Papers, pp. 15-18.
8. 0.3As Quantum Well Transistor on Silicon Substrate using Thin (≤ 2um) Composite Buffer Architecture for High-Speed and Low-Voltage (0.5V) Logic Applications," International Electron Devices Meeting (IEDM) Technical Digest, 2007, pp. 625-628.