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Volumn , Issue , 2008, Pages 161-164

Digital correction of dynamic track-and-hold errors providing SFDR > 83 dB up to fm = 470 MHz

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL CORRECTIONS; DIGITAL TECHNIQUES; DYNAMIC TRACKS; HIGH RESOLUTIONS; NON LINEARITIES; POST-PROCESSING;

EID: 57849107226     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2008.4672048     Document Type: Conference Paper
Times cited : (8)

References (11)
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    • A.M.A. Ali et al., "A 14bit 125Ms/s IF/RF sampling pipelined A/D converter," Proc. CICC, pp. 391-94, Sept. 2005.
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  • 2
    • 0034429530 scopus 로고    scopus 로고
    • A 3.3V, 12b, 50MSample/s A/D converter in 0.6um CMOS with over 80dB SFDR
    • Feb
    • H. Pan et al., "A 3.3V, 12b, 50MSample/s A/D converter in 0.6um CMOS with over 80dB SFDR," ISSCC Dig. Tech. Papers, pp. 4041, Feb. 2000.
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    • Pan, H.1
  • 3
    • 0348233280 scopus 로고    scopus 로고
    • A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification
    • Dec
    • B. Murmann and B. E. Boser, " A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification," IEEE J. Solid-State Circuits, pp. 2040-2050, Dec. 2003.
    • (2003) IEEE J. Solid-State Circuits , pp. 2040-2050
    • Murmann, B.1    Boser, B.E.2
  • 4
    • 4644297975 scopus 로고    scopus 로고
    • Least Mean Square adaptive digital background calibration of pipelined analog-to-digital converters
    • Jan
    • Y. Chiu, et al., "Least Mean Square adaptive digital background calibration of pipelined analog-to-digital converters," IEEE Trans. Ckts Syst. I, pp. 38-46, Jan 2004.
    • (2004) IEEE Trans. Ckts Syst. I , pp. 38-46
    • Chiu, Y.1
  • 5
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    • A 12 b 80 MS/s pipelined ADC with bootstrapped digital calibration
    • Feb
    • C. Grace, P.J. Hurst and S.H. Lewis, "A 12 b 80 MS/s pipelined ADC with bootstrapped digital calibration," ISSCC Dig. Tech. Papers, pp. 460-461, Feb. 2004.
    • (2004) ISSCC Dig. Tech. Papers , pp. 460-461
    • Grace, C.1    Hurst, P.J.2    Lewis, S.H.3
  • 6
    • 66949119191 scopus 로고    scopus 로고
    • National Semiconductor, Online
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    • ADC14155 Datasheet
  • 7
    • 0035693618 scopus 로고    scopus 로고
    • A 3-V 340-mW 14-b 75-MSample/s CMOS ADC With 85-dB SFDR at Nyquist Input
    • Dec
    • W. Yang, et al., "A 3-V 340-mW 14-b 75-MSample/s CMOS ADC With 85-dB SFDR at Nyquist Input," IEEE J. Solid-State Circuits, pp. 1931-1936, Dec. 2001.
    • (2001) IEEE J. Solid-State Circuits , pp. 1931-1936
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  • 8
    • 0032664038 scopus 로고    scopus 로고
    • A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
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    • A.M. Abo and P.R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter," IEEE J. Solid-Stats Circuits, pp.599-606, May 1999.
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  • 10
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    • A 20-GSample/s 8b ADC with a 1-MByte Memory in 0.18-um CMOS
    • Feb
    • K. Poulton et al., "A 20-GSample/s 8b ADC with a 1-MByte Memory in 0.18-um CMOS," ISSCC Dig. Tech. Papers, pp 318-319, Feb. 2003.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.