A 3.3V, 12b, 50MSample/s A/D converter in 0.6μm CMOS with over 80dB SFDR

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 40-41

  Pan, H ^a   Segami, M ^a   Choi, M ^a   Cao, J ^a   Hatori, F ^a   Abidi, A ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER SIMULATION; DIGITAL FILTERS; MONTE CARLO METHODS; TELECOMMUNICATION EQUIPMENT; TIMING JITTER; WIRELESS TELECOMMUNICATION SYSTEMS;

WIRELESS BASE STATIONS;

ANALOG TO DIGITAL CONVERSION;

EID: 0034429530     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. 12b 50MSample/s two-stage A/D converter
2. 2