An 81Gb/s, 1.2V TIALA-retimer in standard 65nm CMOS

2008 IEEE CSIC Symposium: GaAs ICs Celebrate 30 Years in Monterey, Technical Digest 2008

Volumn , Issue , 2008, Pages

  Shahramian, Shahriar ^a   Carusone, Anthony Chan ^a   Schvan, Peter ^b   Voinigescu, Sorin P ^a  

^a UNIVERSITY OF TORONTO   (Canada)

^b NORTEL NETWORKS   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BROADBAND AMPLIFIERS; DIFFERENTIAL AMPLIFIERS; GALLIUM ALLOYS; JITTER; SEMICONDUCTOR DEVICE MANUFACTURE;

CLOCK PATHS; INVERTER BASED; MOS FETS; POWER CONSUMPTIONS; PRE-AMPLIFIERS; RETIMING; SEMICONDUCTOR TECHNOLOGIES; TRANSIMPEDANCE AMPLIFIERS; WAFER MEASUREMENTS;

SEMICONDUCTING GALLIUM;

EID: 57849090163     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CSICS.2008.51     Document Type: Conference Paper

References (5)

1. D. Lim, et al., "Performance variability of a 90 GHz static CML frequency divider in 65nm SOI CMOS technology," ISSCC, pp. 542-621, Feb. 2007
2. T. Suzuki, et al., "A 80-Gbit/s D-Type Flip-Flop Circuit Using InP HEMT Technology," IEEE, JSSC, Vol. 39, No. 10, pp. 1706-1711, Oct. 2004
3. S. Voinigescu, et al., "Towards a sub-2.5V, 100-Gb/s Serial Transceiver," CICC, pp. 471-478, Sept. 2007
4. T. Chalvatzis, et al., "Low voltage topologies for 40+ Gb/s circuits in nanoscale CMOS," IEEE, JSSC, Vol.42, No. 7, pp. 1564-1573, July. 2007
5. T.O. Dickson, et al., "Low-power circuits for a 10.7-to-86 Gb/s serial transmitter in 130-nm SiGe BiCMOS," IEEE, JSSC, Vol. 42, No. 10, pp. 2077-2085, Oct. 2007