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Volumn , Issue , 2008, Pages
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100 Gbit/s fully integrated InP DHBT-based CDR/1:2 DEMUXIC
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Author keywords
Clock and data recovery (CDR); Demultiplexer (DEMUX); Half rate linear phase detector; Inp double heterostructure bipolar transistor (DHBT); Integrated circuit (IC); Loop filter; Voltage controlled oscillator (VCO)
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Indexed keywords
ANTENNA PHASED ARRAYS;
BIPOLAR TRANSISTORS;
CLOCKS;
DEMULTIPLEXING;
DETECTORS;
GALLIUM ALLOYS;
INTEGRATED CIRCUITS;
JITTER;
LINEAR INTEGRATED CIRCUITS;
NETWORKS (CIRCUITS);
PHASE LOCKED LOOPS;
SEMICONDUCTING GALLIUM;
SIGNAL DETECTION;
SIGNAL FILTERING AND PREDICTION;
TRANSISTORS;
VARIABLE FREQUENCY OSCILLATORS;
VELOCITY MEASUREMENT;
CLOCK AND DATA RECOVERY (CDR);
DEMULTIPLEXER (DEMUX);
HALF-RATE LINEAR PHASE DETECTOR;
INP DOUBLE HETEROSTRUCTURE BIPOLAR TRANSISTOR (DHBT);
LOOP FILTER;
VOLTAGE CONTROLLED OSCILLATOR (VCO);
TIMING CIRCUITS;
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EID: 57849087865
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/CSICS.2008.36 Document Type: Conference Paper |
Times cited : (17)
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References (7)
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