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Volumn , Issue , 2008, Pages

100 Gbit/s fully integrated InP DHBT-based CDR/1:2 DEMUXIC

Author keywords

Clock and data recovery (CDR); Demultiplexer (DEMUX); Half rate linear phase detector; Inp double heterostructure bipolar transistor (DHBT); Integrated circuit (IC); Loop filter; Voltage controlled oscillator (VCO)

Indexed keywords

ANTENNA PHASED ARRAYS; BIPOLAR TRANSISTORS; CLOCKS; DEMULTIPLEXING; DETECTORS; GALLIUM ALLOYS; INTEGRATED CIRCUITS; JITTER; LINEAR INTEGRATED CIRCUITS; NETWORKS (CIRCUITS); PHASE LOCKED LOOPS; SEMICONDUCTING GALLIUM; SIGNAL DETECTION; SIGNAL FILTERING AND PREDICTION; TRANSISTORS; VARIABLE FREQUENCY OSCILLATORS; VELOCITY MEASUREMENT;

EID: 57849087865     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CSICS.2008.36     Document Type: Conference Paper
Times cited : (17)

References (7)
  • 3
    • 57849098456 scopus 로고    scopus 로고
    • Over-100-Gb/s 1:2 Demultiplexer based on InP HBT Technology
    • Nov
    • Y. Suzuki, M. Mamada, and Z. Yamazaki, "Over-100-Gb/s 1:2 Demultiplexer based on InP HBT Technology," IEEE Journal of Solid-States Circuit, vol. 42, pp. 2594-2599, Nov. 2007.
    • (2007) IEEE Journal of Solid-States Circuit , vol.42 , pp. 2594-2599
    • Suzuki, Y.1    Mamada, M.2    Yamazaki, Z.3
  • 6
    • 70149103626 scopus 로고    scopus 로고
    • th International Conference on InP and Related Materials, paper TuB 2.2, May 2008.
    • th International Conference on InP and Related Materials, paper TuB 2.2, May 2008.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.