A voltage scalable 0.26V, 64kb 8T SRAM with vmin lowering techniques and deep sleep mode

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2008, Pages 407-410

  Kim, Tae Hyoung ^a   Liu, Jason ^a   Kim, Chris H ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

STATIC RANDOM ACCESS STORAGE;

BIT LINES; BITLINE ANDS; CMOS PROCESSES; LEAKAGE COMPENSATIONS; PULSE WIDTH CONTROLS; READ OPERATIONS; READ PERFORMANCES; SHORT-CHANNEL EFFECTS; SLEEP MODES; STAND-BY LEAKAGES; WORD LINES; WRITE MARGINS;

INTEGRATED CIRCUITS;

EID: 57849085783     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2008.4672106     Document Type: Conference Paper

References (10)

1. H. Kim, H. Soeleman, K. Roy, "An ultra-low power DLMS filter for hearing aid applications", IEEE Trans. VLSI Systems, Volume 11, pp. 1058-1067, Dec. 2003.
2. A. Bryant, J. Brown, P. Cottrell, et al., "Low-power CMOS at Vdd=4kT/q", Device Research Conference, pp. 22-23, 2001.
3. B. Zhai, S. Hanson, D. Blaauw, D. Sylvester, "Analysis and mitigation of variability in subthreshold design", International Symposium on Low Power Electronics and Design, pp. 20-25, Aug. 2005.
4. A. Wang, A.P. Chandrakasan, "A 180-mV subthreshold FFT processor using a minimum, energy design methodology", IEEE J. of Solid-State Circuits, Volume 40, pp. 310-319, Jan. 2005.
5. L. Chang, Y. Nakamura, R.K. Montoye, J. Sawada, et al., "A 5.3GHz 8T-SRAM: with operation down to 0.41V in 65nm CMOS", VLSI Circuits Symposium, pp. 252-253, June 2007.
6. B.H. Calhoun, A. Chandrakasan, "A 256kb Sub-threshold SRAM using 65 nm. CMOS," International Solid-State Circuits Conference, pp. 628-629, Feb. 2006.
7. L. Chang, D.M. Fried, J. Hergenrother, J.W. Sleight, et al., "Stable SRAM cell design for the 32 nm node and beyond," Symposium on VLSI Technology, pp. 128-129, June 2005.
8. J. Chen, L. T. Clark, T. Chen, "An Ultra-Low-Power Memory with a Subthreshold Power Supply Voltage," IEEE J. of Solid-State Circuits, Volume 41, pp. 2344-2353, Oct. 2006.
9. T. Kim, J. Liu, J. Keane, C. Kim, "A high-density subthreshold SRAM with data-independent bitline leakage and virtual ground replica scheme", International Solid-State Circuits Conference, pp. 330-331, Feb. 2007.
10. T. Kim, J. Liu, C. Kim, "An 8T Subthreshold SRAM Cell Utilizing Reverse Short Channel Effect for Write Margin and Read Performance Improvement", Custom Integrated Circuits Conference, pp. 241-244, Oct. 2007.