Fault tolerant system design method based on self-checking circuits

Proceedings - IOLTS 2006: 12th IEEE International On-Line Testing Symposium

Volumn 2006, Issue , 2006, Pages 185-186

  Kubalík, Pavel ^a   Fišer, Petr ^a   Kubátová, Hana ^a  

^a CZECH TECHNICAL UNIVERSITY IN PRAGUE   (Czech Republic)

Author keywords

[No Author keywords available]

Indexed keywords

MULTIPLE PARITY GROUPS; PARITY PREDICTOR DESIGNS; SELF-CHECKING CIRCUITS;

BUILT-IN SELF TEST; FAULT TOLERANT COMPUTER SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

DIGITAL CIRCUITS;

EID: 34247281122     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2006.37     Document Type: Conference Paper

References (8)

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