Frequency planning for multi-core processors under thermal constraints

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2008, Pages 213-216

  Kadin, Michael ^a   Reda, Sherief ^a  

^a Brown University   (United States)

Author keywords

Algorithms; Design; Performance

Indexed keywords

ALGORITHMS; COMBINATORIAL OPTIMIZATION TECHNIQUES; DESIGN COMPLEXITY; DESIGN CONSTRAINTS; DEVELOPED MODELS; FREQUENCY PLANNING; MANY CORES; MAXIMUM TEMPERATURES; MULTI-CORE PROCESSORS; OPERATING CONDITIONS; PERFORMANCE; PERFORMANCE LIMITS; POWER MODELING; SUPERVISED MACHINE LEARNING; TECHNOLOGY SCALING; THERMAL CHARACTERIZATIONS; THERMAL CONSTRAINTS; THERMAL SIMULATION TOOLS; TOTAL PERFORMANCE;

COMBINATORIAL MATHEMATICS; COMBINATORIAL OPTIMIZATION; DESIGN; LEARNING ALGORITHMS; LEARNING SYSTEMS; LOW POWER ELECTRONICS; POWER ELECTRONICS;

MACHINE DESIGN;

EID: 57549084081     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1393921.1393977     Document Type: Conference Paper

References (12)

1. "International Technology Roadmap for Semiconductors." [Online]. Available: http://public.itrs.net
2. J. Boyd, "Native Quad Core Joins X86 Fray," in EETimes.com, 10/01/2007.
3. D. Brooks and M. Martonosi, "Dynamic Thermal Management for High-Performance Microprocessors," in HPCA, 2001, pp. 171-182.
4. D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A Framework for Architectural-Level Power Analysis and Optimizations," in ISCA, 2000, pp. 83-94.
5. J. Donald and M. Martonosi, "Techniques for Multicore Thermal Management: Classification and New Exploration," in ISCA, 2006, pp. 78-88.
6. W. Liao, L. He, and K. Lepak, "Temperature and Supply Voltage Aware Performance and Power Modeling at Microarchitecture Level," Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24(7), pp. 1042-1053, 2005.
7. G. Magklis, G. Semeraro, D. H. Albonesi, S. G. Dropsho, S. Dwarkadas, and M. L. Scott, "Dynamic Frequency and Voltage Scaling for A Multiple-Clock-Domain Microprocessor," IEEE Micro, vol. 23(6), pp. 62-68, 2003.
8. R. Mukherjee and S. O. Memik, "Physical Aware Frequency Selection for Dynamic Thermal Management in Multi-Core Systems," in ICCAD, 2006, pp. 547-552.
9. S. Murali, A. Mutapcic, D. Atienza, R. Gupta, S. Boyd, and G. D. Micheli, "Temperature-Aware Processor Frequency Assignment for MPSoCs Using Convext Optimization," in CODES+ISSS, 2007, pp. 111-116.
10. R. Rao, S. Vrudhula, and C. Chakrabarti, "Throughput of Multi-Core Processors Under Thermal Constraints," in ISLPED, 2007, pp. 201-206.
11. K. Skadron, S. Ghosh, S. Velusamy, K. Sankaranarayanan, and M. Stan, "HotSpot: A Compact Thermal Modeling Methodology for Early-Stage VLSI Design," Transactions on VLSI Systems, vol. 15(5), pp. 501-513, 2006.
12. S. Wilton and N. P. Jouppi, "CACTI: An Enhanced Cache Access and Cycle Time Model," IEEE Journal Solid-State Circuits, vol. 31(5), pp. 677-688, 1996.