A 4.5 GHz to 5.8 GHz tunable ΔΣ digital receiver with enhancement

IEEE MTT-S International Microwave Symposium Digest

Volumn , Issue , 2008, Pages 193-196

  Chalvatzis, Theodoras ^a,b   Voinigescu, Sorin P ^a  

^a UNIVERSITY OF TORONTO   (Canada)

^b BROADCOM CORPORATION   (United States)

Author keywords

Analog to digital converter; Bandpass; Continuous time; Delta sigma; Direct sampling

Indexed keywords

CONTINUOUS TIME SYSTEMS; DIGITAL ARITHMETIC; LOCAL AREA NETWORKS; MICROWAVES; MULTICARRIER MODULATION; NETWORKS (CIRCUITS); SAMPLING; TELECOMMUNICATION SYSTEMS; WIRELESS LOCAL AREA NETWORKS (WLAN);

ANALOG-TO-DIGITAL CONVERTER; BANDPASS; CONTINUOUS-TIME; DELTA-SIGMA; DIRECT SAMPLING;

DIGITAL RADIO;

EID: 57349156697     PISSN: 0149645X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSYM.2008.4633136     Document Type: Conference Paper

References (6)

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2. T. Kaplan, J. Cruz-Albrecht, M. Mokhtari, D. Matthews, J. Jensen, and M. F. Chang, "A 1.3-GHz IF digitizer using a 4th order continuous-time bandpass ΔΣ modulator," in Proc. Custom IC Conf, San Jose, CA, Sep. 2003, pp. 127-130.
3. B. K. Thandri and J. Silva-Martinez, "A 63 dB, 75-mW bandpass RF ΔΣ ADC at 950 MHz using 3.8-GHz clock in 0.25-μm SiGe BiCMOS technology," IEEE J. Solid-State Circuits, vol. 42, pp. 269-279, Feb. 2007.
4. T. Chalvatzis, E. Gagnon, M. Repeta, and S. P. Voinigescu, "A low-noise 40-GS/s continuous-time bandpass ΔΣ ADC centered at 2 GHz for direct sampling receivers," IEEE J. Solid-State Circuits, vol. 42, pp. 1065-1075, May 2007.
5. T. Chalvatzis, T. O. Dickson, and S. P. Voinigescu, "A 2-GHz direct sampling ΔΣ tunable receiver with 40-GHz sampling clock and on-chip PLL," in VLSI Circuits Symposium Tech. Digest, Kyoto, Japan, June 2007, pp. 54-55.
6. T. O. Dickson and S. P. Voinigescu, "Low-power circuits for a 10.7-to-86 Gb/s 80-Gb/s serial transmitter in 130-nm SiGe BiCMOS," in Compound Semiconductor IC Symp. Tech. Digest, San Antonio, TX, Nov. 2006, pp. 235-238.