A 2-GHz direct sampling delta-sigma tunable receiver with 40-GHz sampling clock and on-chip PLL

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 54-55

  Chalvatzis, T ^a   Dickson, T O ^a,b   Voinigescu, S P ^a  

^a UNIVERSITY OF TORONTO   (Canada)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BICMOS TECHNOLOGY; DEGRADATION; SAMPLING;

SAMPLING CLOCK; SNDR DEGRADATION; TUNABLE DIRECT SAMPLING;

MICROPROCESSOR CHIPS;

EID: 39749188149     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342763     Document Type: Conference Paper

References (5)

1. T. Chalvntzis and S. P. Voinigescu. "A Low-Noise 40-GS/s Continuous-Time Bandpass △Σ ADC Centered at 2 GHz," RFIC Symp. Tech. Digest, June 2006, pp. 323-326.
2. T. O. Dickson and S. P. Voinigescu, "Low-power circuits for a 10.7-to-86 Gb/s 80-Gb/s serial transmitter in 130-nm SiGe BiCMOS," CSICS Tech. Digest, Nov. 2006. pp. 235-238.
3. S. Krishnan et al., "An 8-GHz continuous-time Σ-△ analog-digital convener in an InP-based HBT technology," IEEE Trans. MTT, vol. 51, pp 2555-2561, Dec. 2003.
4. th order continuous-time bandpass △Σ modulator," Proc. CICC, Sept. 2003, pp. 127-130.
5. L. Luh et al., "A 4GHz 4th-order Passive LC Bandpass Delta-Sigma Modulator with IP at 1.4GHz," VLSI Symp. Tech. Digest, June 2006, pp. 168-169.