Sequential equivalence checking between system level and RTL descriptions

Design Automation for Embedded Systems

Volumn 12, Issue 4, 2008, Pages 377-396

  Vasudevan, Shobha ^a   Viswanath, Vinod ^c   Abraham, Jacob A ^b   Tu, Jiajin ^b  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b The University of Texas at Austin   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

C vs RTL; SAT solvers; Sequential equivalence checking; Static analysis of hardware

Indexed keywords

DECISION THEORY; DECODING; DESIGN; EQUIVALENCE CLASSES; LINGUISTICS; SEQUENTIAL CIRCUITS; VITERBI ALGORITHM;

C VS RTL; CASE STUDIES; DESIGN BEHAVIORS; EQUIVALENCE CHECKING; EQUIVALENCE CHECKS; FUNCTIONAL MAPPINGS; HARDWARE DESCRIPTION LANGUAGES; REGISTER TRANSFER LEVELS; RTL IMPLEMENTATIONS; SAT SOLVERS; SEQUENTIAL EQUIVALENCE CHECKING; SYMBOLIC EXPRESSIONS; SYSTEM LEVELS; SYSTEMS ON A CHIPS; TECHNIQUES USES; VERILOG; VITERBI DECODERS;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 57349155550     PISSN: 09295585     EISSN: 15728080     Source Type: Journal    
DOI: 10.1007/s10617-008-9033-z     Document Type: Article

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