Automatic verification of arithmetic circuits in RTL using stepwise refinement of term rewriting systems

IEEE Transactions on Computers

Volumn 56, Issue 10, 2007, Pages 1401-1414

  Vasudevan, Shobha ^a   Viswanath, Vinod ^a   Sumners, Robert W ^a   Abraham, Jacob A ^a  

^a The University of Texas at Austin   (United States)

Author keywords

Arithmetic logic unit; Hardware description languages; Register transfer level implementation; Verification

Indexed keywords

COMPUTER CIRCUITS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; MULTIPLYING CIRCUITS; VERIFICATION;

REGISTER TRANSFER LEVEL; STEPWISE REFINEMENT; TERM REWRITING SYSTEM;

DIGITAL ARITHMETIC;

EID: 34548775713     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2007.1073     Document Type: Article

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