High-performance, low-power, and leakage-tolerance challenges for sub-70nm microprocessor circuits

European Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 315-321

  Krishnamurthy, Ram K ^a   Alvandpour, Atila ^a   Mathew, Sanu ^a   Anders, Mark ^a   De, Vivek ^a   Borkar, Shekhar ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT TECHNIQUES; DATAPATH CIRCUITS; DESIGN CHALLENGES; INSTRUCTION SCHEDULER; LEAKAGE POWER DISSIPATIONS; LEAKAGE TOLERANCE; ON CHIP INTERCONNECT; PARADIGM SHIFTS;

CMOS INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS;

LOW POWER ELECTRONICS;

EID: 56849087982     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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