60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 11, 2000, Pages 1713-1721

  Takahashi, Masafumi ^a   Nishikawa, Tsuyoshi ^a,c   Hamada, Mototsugu ^a   Takayanagi, Toshinar ^a,c   Arakida, Hideho ^a,b   Machida, Noriaki ^a,d,e   Yamamoto, Hideaki ^a,f   Fujiyoshi, Toshihide ^a,c   Ohashi, Yoko ^a,g   Yamagishi, Osamu ^a,h   Samata, Tatsuo ^a,i,j   Asano, Atsushi ^a   Terazawa, Toshihiro ^a   Ohmori, Kenji ^a   Watanabe, Yoshinori ^a   Nakamura, Hiroki ^a   Minami, Shigenobu ^a   Kuroda, Tadahiro ^b   Furuyama, Tohru ^a  

^a TOSHIBA CORPORATION   (Japan)

^b KEIO UNIVERSITY   (Japan)

^c UNIVERSITY OF TOKYO   (Japan)

^d WASEDA UNIVERSITY   (Japan)

^e University of Tokyo ^*  (Japan)

^f OSAKA UNIVERSITY   (Japan)

^g KYUSHU UNIVERSITY   (Japan)

^h KOGAKUIN UNIVERSITY   (Japan)

ⁱ TOKAI UNIVERSITY   (Japan)

^j Phetchaburi Institute of Technology   (Thailand)

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Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEMULTIPLEXING; DYNAMIC RANDOM ACCESS STORAGE; IMAGE CODING; INTERFACES (COMPUTER); LEAKAGE CURRENTS; MULTIPLEXING; SPEECH CODING; STANDARDS; THRESHOLD VOLTAGE;

NETWORK INTERFACES; SPEECH CODEC;

LSI CIRCUITS;

EID: 0034316132     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.881219     Document Type: Article

References (3)

1. M. Takahashi et al., "A 60 mW MPEG-4 video codec using clustered voltage scaling with variable supply-voltage scheme," IEEE J. Solid-State Circuits, vol. 33, pp. 1772-1780, Nov. 1998.
2. T. Nishikawa et al., "A 60-MHz 240-mW MPEG-4 video-phone LSI with 16-Mb embedded DRAM," in ISSCC Dig. Tech. Papers, Feb. 2000, pp. 230-231.
3. 2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme," in IEEE ISSCC Dig. Tech. Papers, Feb. 1997, pp. 166-167.