Using an artificial neural network prediction model to optimize work-in-process inventory level for wafer fabrication

Expert Systems with Applications

Volumn 36, Issue 2 PART 2, 2009, Pages 3421-3427

  Lin, Yu Hsin ^a   Shie, Jie Ren ^a   Tsai, Chih Hung ^b  

^a MINGHSIN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Taiwan)

^b TA HWA INSTITUTE OF TECHNOLOGY   (Taiwan)

Author keywords

Neural network; Sequential quadratic programming; Work in process level

Indexed keywords

NEURAL NETWORKS; QUADRATIC PROGRAMMING;

NEURAL NETWORK PREDICTION MODEL; SEQUENTIAL QUADRATIC PROGRAMMING; SEQUENTIAL QUADRATIC PROGRAMMING METHOD; STANDARD DEVIATION; THROUGHPUT RATE; WAFER FABRICATIONS; WORK IN PROCESS INVENTORIES; WORK-IN-PROCESS LEVEL;

FABRICATION;

EID: 56749178304     PISSN: 09574174     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.eswa.2008.02.009     Document Type: Article

References (28)

1. Atherton R.W., and Dayhoff J.E. Signature analysis: Simulation of inventory, cycle time, and throughput trade-offs in wafer fabrication. IEEE Transactions on Components, Hybrids, and Manufacturing Technology 9 (1986) 498-507
2. Burman D.Y., Gurrola-Gal F.J., Nozari A., Sathaye S., and Sitarik J.P. Performance analysis techniques for IC manufacturing lines. AT& T Technical Journal 65 (1986) 46-57
3. Buzacott J.A. The role of banks in flow-line production systems. Internal Journal of Production Research 9 4 (1971) 425-436
4. Connors D.P., Feigin G.E., and Yao D.D. A queueing network model for semiconductor manufacturing. IEEE Transactions on Semiconductor Manufacturing 9 2 (1996) 412-427
5. Das P. Concurrent optimization of multi-response product performance. Quality Engineering 11 (1999) 365-368
6. Dayhoff, J. E., & Atherton, R. W. (1984). Simulation of VLSI manufacturing areas. VLSI Design (pp. 84-92).
7. Egorov-Yegorov I.N., and Dulikravich G.S. Chemical composition design of superalloys for maximum stress, temperature, and time-to-rupture using self-adapting response surface optimization. Materials and Manufacturing Processes 20 3 (2005) 569-590
8. Fletcher R. Practical methods of optimizations, Vol. 1, unconstrained optimization, and Vol. 2, constrained optimization (1981), John Wiley and Sons Inc, New York
9. Glassey C.R., and Resende M.G.C. Closed-loop job release control for VLSI circuit manufacturing. IEEE Transactions on Semiconductor Manufacturing 1 1 (1988) 36-46
10. Glassey C.R., and Resende M.G.C. A scheduling rule for job shop release in semiconductor fabrication. Operations Research Letters 7 5 (1988) 213-217
11. Glassey C.R., and Weng W.W. Dynamic batching heuristic for simultaneous processing. IEEE Transactions on Semiconductor Manufacturing 4 2 (1991) 77-82
12. Huang S.H., and Zhang H.C. Neural-expert hybrid approach for intelligent manufacturing: A survey. Computers in Industry 26 2 (1995) 107-126
13. Huang C.L., Huang Y.H., Chang T.Y., Chang S.H., Chung C.H., Huang D.T., et al. The construction of production performance system for semiconductor manufacturing with artificial neural networks. International Journal of Production Research 37 6 (1999) 1387-1402
14. Law A.M., and Kelton W.D. Simulation modeling & analyses (1991), McGraw-Hill Inc., Singapore
15. Leachman R.C., and Hodges D.A. Benchmarking semiconductor manufacturing. IEEE Transactions on Semiconductor Manufacturing 9 2 (1996) 158-169
16. Liao H.C. A data envelopment analysis method for optimizing multi-response problem with censored data in the Taguchi method. Computer and Industrial Engineering 46 (2004) 817-835
17. Lin Y.H., Chiu C.C., and Tsai C.H. The study of applying anp model to assess dispatching rules for wafer fabrication. Expert Systems with Applications 34 3 (2008) 2148-2163
18. Lin Y.H., and Lee C.E. The total standard WIP estimation method for wafer fabrication. European Journal of Operational Research 131 1 (2001) 78-94
19. Mackay D.J.C. Bayesian interpolation. Neural Computation 3 (1992) 415-447
20. MathWorks Inc. (1997). Neural network toolbox user's guide version. 3.0., 24 Prime Park Way, Natick, MA.
21. Miller D.J. Simulation of a semiconductor manufacturing line. Communications of The ACM 33 10 (1990) 99-108
22. Myers R.H., and Montgomery D.C. Response surface methodology (2002), John Wiley and Sons Inc, New York
23. Qiu R.G. Virtual production line based WIP control for semiconductor manufacturing systems. International Journal of Production Economics 95 (2005) 165-178
24. Suri R., Diehl G.W.W., de Treville S., and Tomsicek M.J. From CAN-Q to MPX: evolution of qneuing software for manufacturing. Interfaces 25 5 (1995) 128-150
25. Tong L.I., Su C.T., and Wang C.H. The optimization of multi-response problems in Taguchi method. International Journal of Quality and Reliability Management 14 (1997) 367-380
26. Tsai C.H., Chang G.T., and Li R.K. Integrating order release control with due-date assignment rules. International Journal of Production Research 35 12 (1997) 3379-3392
27. Udo G.J. Neural networks applications in manufacturing processes. Computers & Industrial Engineering 23 1 (1992) 97-100
28. Wein L.M. Scheduling semiconductor wafer fabrication. IEEE Transactions on Semiconductor Manufacturing 1 3 (1988) 115-130