Total standard WIP estimation method for wafer fabrication

European Journal of Operational Research

Volumn 131, Issue 1, 2001, Pages 78-94

  Lin, Yu Hsin ^a,b   Lee, Ching En ^b  

^a TA HWA INSTITUTE OF TECHNOLOGY   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; INVENTORY CONTROL; LIFE CYCLE; MATHEMATICAL MODELS; PROCESS ENGINEERING; PRODUCTION ENGINEERING; QUEUEING THEORY; RESOURCE ALLOCATION; SEMICONDUCTOR DEVICE MANUFACTURE; STRATEGIC PLANNING;

WAFER FABRICATION; WORK-IN-PROCESS (WIP) ESTIMATION METHOD;

OPERATIONS RESEARCH;

EID: 0035342034     PISSN: 03772217     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0377-2217(99)00446-4     Document Type: Article

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