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Volumn , Issue , 2005, Pages 105-108

A sparsified vector potential equivalent circuit model for massively coupled interconnects

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION COMPLEXITY; COUPLED INTERCONNECTS; EQUIVALENT CIRCUIT MODEL; EXTRACTION TIME; INDUCTANCE MATRIX; INTERPOLATION ALGORITHMS; ORDERS OF MAGNITUDE; PEEC MODELS; SPARSIFICATION; VECTOR POTENTIAL; VPEC MODEL;

EID: 56749135894     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464535     Document Type: Conference Paper
Times cited : (1)

References (13)
  • 1
    • 0016035432 scopus 로고
    • Equivalent circuits models for three dimensional multiconductor systems
    • A. E. Ruehli, "Equivalent circuits models for three dimensional multiconductor systems," IEEE TMTT, pp. 216-220, 1974.
    • (1974) IEEE TMTT , pp. 216-220
    • Ruehli, A.E.1
  • 2
    • 0030645057 scopus 로고    scopus 로고
    • SPIE: Sparse partial inductance extraction
    • Z. He, M. Celik, and L. Pillegi, "SPIE: Sparse partial inductance extraction," in DAC, pp. 137-140, 1997.
    • (1997) DAC , pp. 137-140
    • He, Z.1    Celik, M.2    Pillegi, L.3
  • 3
    • 0034474751 scopus 로고    scopus 로고
    • How to efficiently capture on-chip inductance effects: Introducing a new circuit element K
    • A. Devgan, H. Ji, and W. Dai, "How to efficiently capture on-chip inductance effects: introducing a new circuit element K," in ICCAD, pp. 150-155, 2000.
    • (2000) ICCAD , pp. 150-155
    • Devgan, A.1    Ji, H.2    Dai, W.3
  • 4
    • 0042694159 scopus 로고    scopus 로고
    • Efficient inductance extraction via windowing
    • M. Beattie and L. Pileggi, "Efficient inductance extraction via windowing," in DATE, pp. 430-436, 2001.
    • (2001) DATE , pp. 430-436
    • Beattie, M.1    Pileggi, L.2
  • 5
    • 0036911569 scopus 로고    scopus 로고
    • Inductwise: Inductance-wise interconnect simulator and extractor
    • T. Chen, C. Luk, and C. Chen, "Inductwise: Inductance-wise interconnect simulator and extractor," ICCAD, pp. 884-894, 2002.
    • (2002) ICCAD , pp. 884-894
    • Chen, T.1    Luk, C.2    Chen, C.3
  • 6
    • 0036916123 scopus 로고    scopus 로고
    • A local circuit topology for inductive parasitics
    • A. Pacelli, "A local circuit topology for inductive parasitics," in ICCAD, pp. 208-214, 2002.
    • (2002) ICCAD , pp. 208-214
    • Pacelli, A.1
  • 7
    • 0041633619 scopus 로고    scopus 로고
    • H. Yu and L. He, Vector potential equivalent circuit based on PEEC inversion, in DAC, 2003.
    • H. Yu and L. He, "Vector potential equivalent circuit based on PEEC inversion," in DAC, 2003.
  • 8
    • 0028498583 scopus 로고
    • FastHenry: A multipole-accelerated 3D inductance extraction program
    • Sept
    • M. Kamon, M. Tsuk, and J. White, "FastHenry: a multipole-accelerated 3D inductance extraction program," IEEE TMTT, pp. 1750-1758, Sept. 1994.
    • (1994) IEEE TMTT , pp. 1750-1758
    • Kamon, M.1    Tsuk, M.2    White, J.3
  • 13
    • 0026255002 scopus 로고
    • FastCap: A multipole accelerated 3D capacitance extraction program
    • K. Narbos and J. White, "FastCap: A multipole accelerated 3D capacitance extraction program," IEEE TCAD, vol. 10, no. 11, pp. 1447-1459, 1991.
    • (1991) IEEE TCAD , vol.10 , Issue.11 , pp. 1447-1459
    • Narbos, K.1    White, J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.