Multilayer stacking technology using wafer-to-wafer stacked method

ACM Journal on Emerging Technologies in Computing Systems

Volumn 4, Issue 4, 2008, Pages

  Miyakawa, Nobuaki ^a   Hashimoto, Eiri ^a   Maebashi, Takanori ^a   Nakamura, Natsuo ^a   Sacho, Yutaka ^a   Nakayama, Shigeto ^a   Toyoda, Shinjiro ^a  

^a HONDA RESEARCH INSTITUTE JAPAN CO LTD   (Japan)

Author keywords

3D integration; Design; Hardware; Stacking process

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CONDUCTIVITY; MULTICHIP MODULES; PROCESS ENGINEERING; SILICON; SILICON WAFERS; TECHNOLOGY; THREE DIMENSIONAL; ZEOLITES;

3D INTEGRATION; CMOS TECHNOLOGIES; ELECTRICAL CONDUCTIVITIES; FUNCTIONAL TESTS; POWER CONSUMPTIONS; STACKING PROCESS; STACKING TECHNOLOGIES;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 56349103207     PISSN: 15504832     EISSN: 15504840     Source Type: Journal    
DOI: 10.1145/1412587.1412593     Document Type: Article

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