A new fabrication method for multi-layer stacked devices using wafer-to-wafer stacked technology based on 8-inch wafers

ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference

Volumn 2007, Issue , 2007, Pages 251-254

  Maebashi, Takanori ^a   Nakamura, Natsuo ^a   Nakayama, Shigeto ^a   Miyakawa, Nobuaki ^a  

^a HONDA RESEARCH INSTITUTE JAPAN CO LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CONDUCTIVITY; ELECTRIC RESISTANCE; INTERCONNECTION NETWORKS;

BURIED INTERCONNECTION (BI); FUNCTIONAL DEVICES; MICRO-BUMPS;

WSI CIRCUITS;

EID: 39549113452     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2007.4430925     Document Type: Conference Paper

References (6)

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3. P.R.Morrow,et al., "Three-Dimensional Wafer Stacking Via Cu-Cu Bonding Integrated With 65-nm Strained-Si/Low-kCMOS Technology," IEEE Electron Device Letters, Vol. 27, No.5, pp335-337, May 2006
4. T. Matsumoto, Y. Kudoh, M. Tahara, K.. H. Yu, N. Miyakawa, H. Itani, T. Ichikizaki, A. Fujiwara, H. Tsukamoto, and M. Koyanagi, "Three dimensional integration technology based on wafer bonding technique using micro-bumps," in Proc. Int. Conf. Solid State Devices and Mater.,1995, pp. 1073-1074.
5. T. Matsumoto, M. Satoh, K. Sakuma, H. Kurino, N. Miyakawa, H. Itani, and M.Koyanagi, "New Three-Dimensional Wafer Bonding Technology Using Adhesive Injection Method," in Proc. Int. Conf. Solid State Devices and Mater., 1997, pp. 460-461.
6. M. Koyanagi, H. Kurino, K. W. Lee, K. Sakuma, N. Miyakawa, and H.Itani, "Future system-on-silicon LSI chips," IEEE Micro, vol. 18, no. 4, pp.l7-22, Jul./Aug. 1998.