On the design of fast pseudo-random number generators for the cell broadband engine and an application to risk analysis

Proceedings of the International Conference on Parallel Processing

Volumn , Issue , 2008, Pages 520-527

  Bader, David A ^a   Chandramowlishwaran, Aparna ^a   Agarwal, Virat ^a  

^a Georgia Institute of Technology

Author keywords

[No Author keywords available]

Indexed keywords

AMD MICROPROCESSORS; AVERAGING METHODS; CELL BROADBAND ENGINES; COMPUTATIONAL PHYSICS; FINANCIAL MARKETS; GAUSSIAN; HIGH QUALITIES; LINEAR CONGRUENTIAL GENERATORS; MERSENNE TWISTERS; MUELLER; NORMALIZATION TECHNIQUES; NUMERICAL SIMULATIONS; PARALLEL IMPLEMENTATIONS; PARALLEL RANDOM NUMBER GENERATORS; PARALLEL STREAMS; PSEUDO RANDOM NUMBER GENERATORS; RANDOM NUMBER GENERATORS; RANDOM NUMBERS; SPEED-UP; VALUE AT RISKS;

NUMBER THEORY; PARALLEL ALGORITHMS; RANDOM PROCESSES; RISK ANALYSIS; RISK ASSESSMENT; RISK MANAGEMENT; SAFETY FACTOR; TELECOMMUNICATION SYSTEMS; TELLURIC PROSPECTING; TRELLIS CODES;

RANDOM NUMBER GENERATION;

EID: 55849100776     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.2008.41     Document Type: Conference Paper

References (23)

1. V. Agarwal, L.-K. Liu, and D. Bader. Financial modeling on the cell broadband engine. In Proc. Int'l Parallel and Distributed Processing Symp. (IPDPS 2008), Miami, FL, Apr. 2008.
2. G. E. P. Box and M. E. Muller. A note on the generation of random normal deviates. The Annals of Mathematical Statistics, 29(2):610-611, 1958.
3. T. Chen, R. Raghavan, J. Dale, and E. Iwata. Cell Broadband Engine Architecture and its first implementation. http://www-128.ibm.com/ developerworks/ power/library/pa-cellperf/, Nov. 2005.
4. B. Flachs, S. Asano, S. Dhong, P. Hotstee, G. Gervais, R. Kim, T. Le, P. Liu, J. Leenstra, J. Liberty, B. Michael, H. Oh, S. Mueller, O. Takahashi, A. Hatakeyama, Y. Watanabe, and N. Yano. A streaming processor unit for a Cell processor. In International Solid State Circuits Conference, volume 1, pages 134-135, San Fransisco, CA, USA, February 2005.
5. R. George. Algorithm 200: normal random. Communications of the ACM, 6(8):444, 1963.
6. H. Hofstee. Cell Broadband Engine Architecture from 20,000 feet. http://www-128.ibm.com/ developerworks/power/library/pa-cbea. html, Aug. 2005.
7. H. Hofstee. Real-time supercomputing and technology for games and entertainment. In Proc. SC, Tampa, FL, Nov. 2006. (Keynote Talk).
8. IBM Corporation. Cell Broadband Engine technology. White paper.
9. IBM Corporation. The Cell project at IBM Research. White paper.
10. J. Kahle, M. Day, H. Hofstee, C. Johns, T. Maeurer, and D. Shippy. Introduction to the Cell multiprocessor. IBM J. Res. Dev., 49(4/5):589-604, 2005.
11. M. Kistler, M. Perrone, and F. Petrini. Cell multiprocessor communication network: Built for speed. IEEE Micro, 26(3): 10-23, 2006.
12. D. Lehmer. Mathematical methods in large-scale computing units. In Proc. 2nd Symp. on Large-Scale Digital Calculating Machinery, pages 141-146, Cambridge, MA, May 1951.
13. G. Marsaglia. A current view of random numbers. In Computer Science and Statistics, Proceedings of the Sixteenth Symposium on The Interface, pages 3-10, North-Holland, Amsterdam, 1985.
14. M. Mascagni. Parallel linear congruential generators with prime moduli. Parallel Computing, 24(5-6):923-936, 1998.
15. M. Mascagni and A. Srinivasan. Algorithm 806: SPRNG: a scalable library for pseudorandom number generation. ACM Trans. Math. Softw., 26(3):436-461, 2000.
16. M. Mascagni, A. Srinivasan, S. Ceperley, and F. Saied. Scalable Parallel Random Number Generators (SPRNG) Library. Florida State University, 2.0 edition, 1995. sprng.cs.fsu.edu.
17. M. Matsumoto and T. Nishimura. Mersenne twister: a 623-dimensionally equidistributed uniform pseudo-random number generator. ACM Trans. Model. Comput. Simul., 8(1):3-30, 1998.
18. M. Matsumoto and T. Nishimura. Dynamic creation of pseudorandom number generators. In Monte Carlo and Quasi-Monte Carlo Methods 1998, pages 56-69. Springer, 2000.
19. D. Pham, E. Behnen, M. Bolliger, H. Hofstee, C. Johns, J. Kahle, A. Kameyama, J. Keaty, B. Le, Y. Masubuchi, S. Posluszny, M. Riley, M. Suzuoki, M. Wang, J. Warnock, S. Weitzel, D. Wendel, and K. Yazawa. The design and implementation of a first-generation Cell processor. In International Solid State Circuits Conference, volume 1, pages 184-185, San Fransisco, CA, USA, February 2005.
20. M. Saito and M. Matsumoto. Simple and fast MT: A two times faster new variant of Mersenne twister. 2006.
21. Sony Corporation. Sony release: Cell architecture. White paper.
22. S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar. An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS. In International Solid State Circuits Conference, pages 29-41, Lille, France, 2007.
23. C. Wallace. A suggestion for a fast multiplier. IEEE Trans. Electronic Computers, EC-13(1): 14-17, Feb. 1964.