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Volumn , Issue , 2006, Pages 369-374

On reconfigurable architectures for efficient matrix inversion

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FUZZY LOGIC; PRODUCT DEVELOPMENT; STANDARDS;

EID: 46249132940     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2006.311239     Document Type: Conference Paper
Times cited : (21)

References (10)
  • 7
    • 34548856953 scopus 로고    scopus 로고
    • Reconfigurable systems for acceleration of matrix operations (in Portuguese),
    • Master's thesis, Technical University of Lisbon, Mar
    • G. Matos, "Reconfigurable systems for acceleration of matrix operations (in Portuguese)," Master's thesis, Technical University of Lisbon, Mar. 2006.
    • (2006)
    • Matos, G.1
  • 8
    • 46249088855 scopus 로고    scopus 로고
    • Alpha-Data, ADM-XRC-II Reconfigurable Computer documentation, 2002, http://www.alpha-data.com/adm-xrcii.html.
    • Alpha-Data, ADM-XRC-II Reconfigurable Computer documentation, 2002, http://www.alpha-data.com/adm-xrcii.html.
  • 9
    • 46249116080 scopus 로고    scopus 로고
    • A. N. S. Institute, IEEE standard for binary floating-point arithmetic. ANSI/IEEE, 1985, technical Report 754-1985.
    • A. N. S. Institute, IEEE standard for binary floating-point arithmetic. ANSI/IEEE, 1985, technical Report 754-1985.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.