FPGA based acceleration of the linpack benchmark: A high level code transformation approach

Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2006, Pages 375-380

  Turkington, Kieron ^a   Masselos, Konstantinos ^a   Constantinides, George A ^a   Leong, Philip ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COSINE TRANSFORMS; FUZZY LOGIC; MICROPROCESSOR CHIPS;

APPLIED (CO); CLOCK FREQUENCIES; CODE TRANSFORMATIONS; EXPERIMENTAL RESULTS; FIELD PROGRAMMABLE GATE ARRAY (FPGA); FIELD PROGRAMMABLE LOGIC (FPL); FLOATING POINT (FP); HANDEL-C; HIGH-LEVEL DESCRIPTIONS; INTERNATIONAL CONFERENCES; LARGE SCALES; LINPACK; LINPACK BENCHMARK; MEMORY MODELING; MEMORY RESOURCES; RE CONFIGURABLE COMPUTING (RCC); SCIENTIFIC APPLICATIONS; SUSTAINED PERFORMANCE;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 46249126438     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2006.311240     Document Type: Conference Paper

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