Modeling avalanche multiplication for advanced high-speed SiGe bipolar transistors

2003 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers

Volumn , Issue , 2003, Pages 18-21

  Pfost, M ^a   Kubrak, V ^a   Romanyuk, A ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

Avalanche breakdown; Bipolar transistors; Breakdown voltage; Circuit simulation; Germanium silicon alloys; High speed optical techniques; Laser radar; Optical fiber networks; Predictive models; Silicon germanium

Indexed keywords

BICMOS TECHNOLOGY; BIPOLAR TRANSISTORS; CIRCUIT SIMULATION; ELECTRIC BREAKDOWN; GERMANIUM; GERMANIUM ALLOYS; HETEROJUNCTION BIPOLAR TRANSISTORS; INTEGRATED CIRCUITS; OPTICAL FIBERS; OPTICAL RADAR; PARAMETER EXTRACTION; SILICON; SILICON ALLOYS; TRANSISTORS;

AVALANCHE BREAKDOWN; GERMANIUM SILICON ALLOY; HIGH SPEED OPTICAL TECHNIQUES; OPTICAL FIBER NETWORKS; PREDICTIVE MODELS; SILICON GERMANIUM;

MONOLITHIC INTEGRATED CIRCUITS;

EID: 5444237676     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SMIC.2003.1196658     Document Type: Conference Paper

References (7)

1. M. Rickelt and H.-M. Rein, "A novel transistor model for simulating avalanche-breakdown effects in Si bipolar circuits," IEEE Journal of Solid-State Circuits, vol. 37, pp. 1184-1197, Sept. 2002.
2. M. Rickelt, H.-M. Rein, and E. Rose, "Influence of impact-ionization-induced instabilities on the maximum usable output voltage of Si-bipolar transistors," IEEE Transactions on Electron Devices, vol. 48, pp. 774-783, Apr. 2001.
3. G. Verzellesi, G. Baccarani, C. Canali, P. Pavan, L. Vendrame, and E. Zanoni, "Prediction of impact-ionization induced snapback in advanced Si n-p-n BJT's by means of a nonlocal analytical model for the avalanche multiplication factor," IEEE Transactions on Electron Devices, vol. 40, pp. 2296-2300, Dec. 1993.
4. G.-B. Hong and J. G. Fossum, "Implementation of nonlocal model for impact-ionization current in bipolar circuit simulation and application to SiGe HBT design optimization," IEEE Transactions on Electron Devices, vol. 42, pp. 1166-1173, June 1995.
5. P.-F. Lu and C. T. Chuang, "Effect of reverse base current on bipolar and BiCMOS circuits," IEEE Transactions on Electron Devices, vol. 39, pp. 1902-1908, Aug. 1992.
6. J. Böck, H. Schäfer, H. Knapp, D. Zöschg, K. Aufinger, M. Wurzer, S. Boguth, M. Rest, R. Schreiter, R. Stengl, and T. F. Meister, "Sub 5ps SiGe bipolar technology," in Proc. IEEE 2002 IEDM, (San Francisco, CA), pp. 763-766, Dec. 2002.
7. G. Niu, J. D. Cressler, S. Zhang, U. Gogineni, and D. C. Ahlgren, "Measurement of collector-base junction avalanche multiplication effects in advanced UHV/CVD SiGe HBT's," IEEE Transactions on Electron Devices, vol. 46, pp. 1007-1015, May 1999.