SCOPUS 정보 검색 플랫폼

Electronics Letters

Volumn 44, Issue 21, 2008, Pages 1225-1226

Efficient switched-capacitor common-mode feedback circuit for high-speed low-power amplifiers

(4) Amoroso, F A a Pugliese, A a Cappuccino, G a Cocorullo, G a

a UNIVERSITY OF CALABRIA (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); ANALOG TO DIGITAL CONVERSION; CAPACITANCE; CAPACITORS; CMOS INTEGRATED CIRCUITS; DIELECTRIC DEVICES; ELECTRIC EQUIPMENT; OPERATIONAL AMPLIFIERS; POWER AMPLIFIERS; SPEED; SWITCHING CIRCUITS;

CAPACITIVE LOADS; CMOS TECHNOLOGIES; COMMON-MODE FEEDBACK; HIGH SPEEDS; LOW POWERS; POWER CONSUMPTION; SETTLING TIME; SIMULATION RESULTS; SPEED PERFORMANCE; SWITCHED CAPACITORS; SWITCHED-CAPACITOR;

BANDPASS AMPLIFIERS;

EID: 53849113667 PISSN: 00135194 EISSN: None Source Type: Journal
DOI: 10.1049/el:20082279 Document Type: Article

Times cited : (6)

References (6)

1
- 38849162117
- A 0.9-V 60-W 1-bit fourth-order delta-sigma modulator with 83-dB dynamic range
- 10.1109/JSSC.2007.914266 0018-9200
- Roh, J., Byun, S., Choi, Y., Roh, H., Kim, Yi-G., and Kwon, J.-L.: ' A 0.9-V 60-W 1-bit fourth-order delta-sigma modulator with 83-dB dynamic range ', IEEE J. Solid-State Circuits, 2008, 43, (2), p. 361-370 10.1109/JSSC.2007.914266 0018-9200
- (2008) IEEE J. Solid-state Circuits , vol.43 , Issue.2 , pp. 361-370
- Roh, J.¹ Byun, S.² Choi, Y.³ Roh, H.⁴ Kim, Y.-G.⁵ Kwon, J.-L.⁶

2
- 34748862291
- A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background calibration
- 10.1109/JSSC.2007.905293 0018-9200
- Lee, Z.-M., Wang, C.-Y., and Wu, J.-T.: ' A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background calibration ', IEEE J. Solid-State Circuits, 2007, 42, (10), p. 2149-2160 10.1109/JSSC.2007.905293 0018-9200
- (2007) IEEE J. Solid-State Circuits , vol.42 , Issue.10 , pp. 2149-2160
- Lee, Z.-M.¹ Wang, C.-Y.² Wu, J.-T.³

3
- 0346707501
- Analysis of switched-capacitor common-mode feedback circuit
- Choksi, O., and Carley, L.R.: ' Analysis of switched-capacitor common-mode feedback circuit ', IEEE Trans. Circ. Syst. II, Analog Digit. Signal Process., 2003, 50, (12), p. 906-917
- (2003) IEEE Trans. Circ. Syst. II, Analog Digit. Signal Process. , vol.50 , Issue.12 , pp. 906-917
- Choksi, O.¹ Carley, L.R.²

4
- 0037168194
- Low-power low-voltage differential class-AB OTAs for SC circuits
- 10.1049/el:20020958 0013-5194
- Carvajal, R.G., Galan, J., Ramìrez-Angulo, J., and Torralba, A.: ' Low-power low-voltage differential class-AB OTAs for SC circuits ', Electron. Lett., 2002, 38, (22), p. 1304-1605 10.1049/el:20020958 0013-5194
- (2002) Electron. Lett. , vol.38 , Issue.22 , pp. 1304-1605
- Carvajal, R.G.¹ Galan, J.² Ramìrez-Angulo, J.³ Torralba, A.⁴

5
- 36049019347
- Parallel correlated double sampling technique for pipelined analogue-to-digital converters
- 10.1049/el:20072152 0013-5194
- Musah, T., Gregoire, B.R., Naviasky, E., and Moon, U.-K.: ' Parallel correlated double sampling technique for pipelined analogue-to-digital converters ', Electron. Lett., 2007, 43, (23), p. 1260-1261 10.1049/el:20072152 0013-5194
- (2007) Electron. Lett. , vol.43 , Issue.23 , pp. 1260-1261
- Musah, T.¹ Gregoire, B.R.² Naviasky, E.³ Moon, U.-K.⁴

6
- 36048979688
- Settling time optimisation for two-stage CMOS amplifiers with current-buffer Miller compensation
- 10.1049/el:20072059 0013-5194
- Pugliese, A., Amoroso, F.A., Cappuccino, G., and Cocorullo, G.: ' Settling time optimisation for two-stage CMOS amplifiers with current-buffer Miller compensation ', Electron. Lett., 2007, 43, (23), p. 1257-1258 10.1049/el:20072059 0013-5194
- (2007) Electron. Lett. , vol.43 , Issue.23 , pp. 1257-1258
- Pugliese, A.¹ Amoroso, F.A.² Cappuccino, G.³ Cocorullo, G.⁴

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.