Parallel correlated double sampling technique for pipelined analogue-to-digital converters

Electronics Letters

Volumn 43, Issue 23, 2007, Pages 1260-1261

  Musah, T ^a   Gregoire, B R ^a   Naviasky, E ^b   Moon, U K ^a  

^a Oregon State University   (United States)

^b Cadence Design Services   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CORRELATION METHODS; GAIN CONTROL; SPURIOUS SIGNAL NOISE;

CORRELATED DOUBLE SAMPLING; SUPERIOR NOISE PERFORMANCE; THERMAL NOISE PENALTY;

ANALOG TO DIGITAL CONVERSION;

EID: 36049019347     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20072152     Document Type: Article

References (3)

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2. Sarhang-Nejad, M., and Temes, G.: ' A high-resolution multi-bit ΣΔ ADC with digital correction and relaxed amplifier requirements ', IEEE J. Solid State Circuits, 1993, 26, (6), p. 648-660
3. Li, J., and Moon, U.: ' A 1.8-V 67-mW 10-bit 100-MS/s pipeline ADC using time-shifted CDS technique ', IEEE J. Solid-State Circuits, 2004, 39, (9), p. 1468-1476 0018-9200