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Electronics Letters
Volumn 43, Issue 23, 2007, Pages 1257-1258
Settling time optimisation for two-stage CMOS amplifiers with current-buffer Miller compensation
Author keywords

[No Author keywords available]
Indexed keywords

BUFFER CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CURRENTS; ERROR ANALYSIS; OPTIMIZATION;
EID: 36048979688     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20072059     Document Type: Article
Times cited : (19)
References (7)
  • 1
    • 1442287577 scopus 로고    scopus 로고
    • Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers
    • et al. 10.1109/TCSI.2003.820254 1057-7122
    • Hurst, P.J.: et al. ' Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers ', IEEE Trans. Circuits Syst. I, 2004, 51, (3), p. 275-285 10.1109/TCSI.2003.820254 1057-7122
    • (2004) IEEE Trans. Circuits Syst. i , vol.51 , Issue.3 , pp. 275-285
    • Hurst, P.J.1
  • 2
    • 0031101679 scopus 로고    scopus 로고
    • A compensation strategy for two-stage CMOS opamps based on current buffer
    • 10.1109/81.557376 1057-7122
    • Palmisano, G., and Palumbo, G.: ' A compensation strategy for two-stage CMOS opamps based on current buffer ', IEEE Trans. Circuits Syst. I, 1997, 44, (3), p. 257-262 10.1109/81.557376 1057-7122
    • (1997) IEEE Trans. Circuits Syst. i , vol.44 , Issue.3 , pp. 257-262
    • Palmisano, G.1    Palumbo, G.2
  • 3
    • 28444498892 scopus 로고    scopus 로고
    • Design procedure for two-stage CMOS operational amplifiers employing current buffer
    • 10.1109/TCSII.2005.852530 1057-7130
    • Mahattanakul, J.: ' Design procedure for two-stage CMOS operational amplifiers employing current buffer ', IEEE Trans. Circuits Syst. II, 2005, 52, (11), p. 766-770 10.1109/TCSII.2005.852530 1057-7130
    • (2005) IEEE Trans. Circuits Syst. II , vol.52 , Issue.11 , pp. 766-770
    • Mahattanakul, J.1
  • 4
    • 0035370406 scopus 로고    scopus 로고
    • Design procedure for two-stage CMOS transconductance operational amplifiers: A tutorial
    • 0925-1030
    • Palmisano, G., Palumbo, G., and Pennisi, S.: ' Design procedure for two-stage CMOS transconductance operational amplifiers: a tutorial ', Analog Integr. Circuits Signal Process., 2001, 27, p. 179-189 0925-1030
    • (2001) Analog Integr. Circuits Signal Process. , vol.27 , pp. 179-189
    • Palmisano, G.1    Palumbo, G.2    Pennisi, S.3
  • 5
    • 0033884138 scopus 로고    scopus 로고
    • Reliable analysis of settling errors in SC integrators: Application to ΣΔ modulators
    • et al. 0013-5194
    • Del Rio, R.: et al. ' Reliable analysis of settling errors in SC integrators: application to ΣΔ modulators ', Electron. Lett., 2000, 36, (6), p. 503-504 0013-5194
    • (2000) Electron. Lett. , vol.36 , Issue.6 , pp. 503-504
    • Del Rio, R.1
  • 6
    • 0016333057 scopus 로고
    • Relationship between frequency response and settling time of operational amplifiers
    • 10.1109/JSSC.1974.1050527 0018-9200
    • Kamath, B.Y., Meyer, R.G., and Gray, P.R.: ' Relationship between frequency response and settling time of operational amplifiers ', IEEE J. Solid-State Circuits, 1974, SC-9, (6), p. 347-352 10.1109/JSSC.1974.1050527 0018-9200
    • (1974) IEEE J. Solid-State Circuits , vol.SC-9 , Issue.6 , pp. 347-352
    • Kamath, B.Y.1    Meyer, R.G.2    Gray, P.R.3
  • 7
    • 0035693267 scopus 로고    scopus 로고
    • A 2.5-V sigma-delta moduator for broadband communications applications
    • 10.1109/4.972139 0018-9200
    • Vleugels, K., Rabii, S., and Wooley, B.A.: ' A 2.5-V sigma-delta moduator for broadband communications applications ', IEEE J. Solid-State Circuits, 2001, 36, (12), p. 1887-1899 10.1109/4.972139 0018-9200
    • (2001) IEEE J. Solid-State Circuits , vol.36 , Issue.12 , pp. 1887-1899
    • Vleugels, K.1    Rabii, S.2    Wooley, B.A.3

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.