Quantifying instruction criticality

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn 2002-January, Issue , 2002, Pages 104-113

  Tune, E S ^a   Tullsen, D M ^a   Calder, B ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Accuracy; Application software; Buildings; Computer science; Counting circuits; Delay; History; Pipelines; Processor scheduling; Runtime

Indexed keywords

APPLICATION PROGRAMS; BUILDINGS; COMPUTER SCIENCE; COUNTING CIRCUITS; DELAY CIRCUITS; HISTORY; PARALLEL ARCHITECTURES; PIPELINES;

ACCURACY; CRITICAL PATHS; DELAY; INDIVIDUAL DYNAMICS; INSTRUCTION CRITICALITIES; PREDICTOR ACCURACY; PROCESSOR SCHEDULING; RUNTIMES;

CRITICALITY (NUCLEAR FISSION);

EID: 52949133622     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2002.1106008     Document Type: Conference Paper

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