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Volumn 3133, Issue , 2004, Pages 224-233

Modeling loop unrolling: Approaches and open issues

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS;

EID: 35048884179     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-27776-7_24     Document Type: Article
Times cited : (11)

References (18)
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    • Mapping a Single Assignment Programming Language to Reconfigurable Systems
    • Kluwer Academic Publishers, Feb.
    • W. Böhm, et al., "Mapping a Single Assignment Programming Language to Reconfigurable Systems," in The Journal of Supercomputing, Kluwer Academic Publishers, vol. 21, no. 2, Feb. 2002, pp. 117-130.
    • (2002) The Journal of Supercomputing , vol.21 , Issue.2 , pp. 117-130
    • Böhm, W.1
  • 4
    • 0042635700 scopus 로고    scopus 로고
    • Using Estimates from Behavioral Synthesis Tools in Compiler-Directed Design Space Exploration
    • June
    • B. So, P. Diniz, and M. Hall, "Using Estimates from Behavioral Synthesis Tools in Compiler-Directed Design Space Exploration", In Proc. of Design Automation Conference (DAC'03), June 2003.
    • (2003) Proc. of Design Automation Conference (DAC'03)
    • So, B.1    Diniz, P.2    Hall, M.3
  • 6
    • 24944454037 scopus 로고    scopus 로고
    • Compilation for Reconfigurable Computing Platforms: Comments on Techniques and Current Status
    • RT/009/2003, Oct.
    • J. Cardoso, P. Diniz, and M. Weinhardt, "Compilation for Reconfigurable Computing Platforms: Comments on Techniques and Current Status," INESC-ID Technical Report, RT/009/2003, Oct. 2003.
    • (2003) INESC-ID Technical Report
    • Cardoso, J.1    Diniz, P.2    Weinhardt, M.3
  • 9
    • 0034174187 scopus 로고    scopus 로고
    • PipeRench: A Reconfigurable Architecture and Compiler
    • April
    • S. Goldstein, et al., "PipeRench: A Reconfigurable Architecture and Compiler," In IEEE Computer, Vol.33, No. 4, April 2000, pp. 70-77.
    • (2000) IEEE Computer , vol.33 , Issue.4 , pp. 70-77
    • Goldstein, S.1
  • 11
    • 79955142752 scopus 로고    scopus 로고
    • XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture
    • Proc. of Int'l Conference on Field Programmable Logic and Applications (FPL'02), Springer-Verlag, Sept.
    • J. Cardoso, and M. Weinhardt, "XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture," in Proc. of Int'l Conference on Field Programmable Logic and Applications (FPL'02), LNCS 2438, Springer-Verlag, Sept. 2002, pp. 864-874.
    • (2002) LNCS , vol.2438 , pp. 864-874
    • Cardoso, J.1    Weinhardt, M.2
  • 12
    • 84893790504 scopus 로고    scopus 로고
    • Accurate Area and Delay Estimators for FPGAs
    • March Paris, France
    • A. Nayak, et al., "Accurate Area and Delay Estimators for FPGAs," in Proc. Design Automation and Test in Europe (DATE'02), March 2002, Paris, France, pp. 862-869.
    • (2002) Proc. Design Automation and Test in Europe (DATE'02) , pp. 862-869
    • Nayak, A.1
  • 13
    • 35248817909 scopus 로고    scopus 로고
    • Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations
    • Proc. of Int'l Conference on Field programmable Logic (FPL'03), Springer-Verlag, Berlin, August
    • J. Park, P. Diniz, and S. Raghunathan, "Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations," In Proc. of Int'l Conference on Field programmable Logic (FPL'03), LNCS, Springer-Verlag, Berlin, August 2003.
    • (2003) LNCS
    • Park, J.1    Diniz, P.2    Raghunathan, S.3
  • 16
    • 35248814419 scopus 로고    scopus 로고
    • A Model for Hardware Realization of Kernel Loops
    • Proc. of 13th Int'l Conference on Field Programmable Logic and Application (FPL'03), Springer-Verlag, Sept.
    • J. Liao, W.F. Wong, and M. Tulika, "A Model for Hardware Realization of Kernel Loops," in Proc. of 13th Int'l Conference on Field Programmable Logic and Application (FPL'03), LNCS 2778, Springer-Verlag, Sept. 2003, pp. 334-344.
    • (2003) LNCS , vol.2778 , pp. 334-344
    • Liao, J.1    Wong, W.F.2    Tulika, M.3
  • 17
    • 35048856534 scopus 로고    scopus 로고
    • Loop Dissevering: A Technique for Temporally Partitioning Loops in Dynamically Reconfigurable Computing Platforms
    • Nice, France, April
    • J. Cardoso, "Loop Dissevering: A Technique for Temporally Partitioning Loops in Dynamically Reconfigurable Computing Platforms," in Proc. of Reconfigurable Architectures Workshop (RAW'03), Nice, France, April 2003.
    • (2003) Proc. of Reconfigurable Architectures Workshop (RAW'03)
    • Cardoso, J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.