A model for hardware realization of kernel loops

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2778, Issue , 2003, Pages 334-344

  Liao, Jirong ^a   Wong, Weng Fai ^a   Mitra, Tulika ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

BUDGET CONTROL; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

APPLICATION PERFORMANCE; DESIGN SPACE EXPLORATION; HARDWARE REALIZATION; IMPLEMENTATION PLATFORMS; LOOP OPTIMIZATIONS; RESOURCE REQUIREMENTS; SOFTWARE PIPELINING; SYNTHESIS PROCESS;

HARDWARE;

EID: 35248814419     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-45234-8_33     Document Type: Article

References (19)

1. Rau, B.R.: Iterative Modulo Scheduling. The International Journal of Parallel Processing 24 (1996)
2. Page, I., Luk, W.: Compiling OCCAM into FPGAs. In: Proceedings of the International Symposium on Field Programmable Logic (FPL). (1991)
3. Rinker, R., et al.: An Automated Process for Compiling Dataflow Graphs into Reconfigurable Hardware. IEEE Transactions on VLSI Systems 9 (2001)
4. Goldstein, S.C., et al.: Piperench: A Reconfigurable Architecture and Compiler. IEEE Computer (2000)
5. Callahan, T., Hauser, J.R., Wawrzynek, J.: The Garp Architecture and C Compiler. IEEE Computer (2000)
6. Weinhardt, M.: Compilation and Pipeline Synthesis for Reconfigurable Architectures. In: Proceedings of the Reconfigurable Architecture Workshop (RAW). (1997)
7. Weinhardt, M., Luk, W.: Pipeline vectorization for reconfigurable systems. In: Proceedings of the IEEE Symposium on Field Programmable Custom Computing Machines (FCCM). (1999)
8. Babb, J., et al.: Parallelizing Applications into Silicon. In: Proceedings of the IEEE Symposium on Field Programmable Custom Computing Machines (FCCM). (1999)
9. Snider, G., Shackleford, B., Carter, R.J.: Attacking the Semantic Gap between Application Programming Languages and Configurable Hardware. In: Proceedings of ACM FPGA. (2001)
10. Jones, A., et al.: PACT HDL: A C Compiler Targeting ASICs and FPGAs with Power and Performance Optimizations. In: Proceedings of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES). (2002)
11. Schreiber, R.: High-Level Synthesis of Nonprogrammable Hardware Accelerators. In: Proceedings of the IEEE International Conference on Application Specific Systems, Architectures, and Processors (ASAP). (2000)
12. Sivaraman, M., Aditya, S.: Cycle-time Aware Architecture Synthesis of Custom Hardware Accelerator. In: Proceedings of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES). (2002)
13. Mentor Graphics Inc.: Mentor Graphics Monet User's Manual (release r42). (1999)
14. Derrien, S., Rajopadhye, S.: Loop Tiling for Reconfigurable Accelerators. In: Proceedings of the International Symposium on Field Programmable Logic (FPL). (2001)
15. So, B., Hall, M.W., Diniz, P.C.: A Compiler Approach to Fast Hardware Design Space Exploration in FPGA-based Systems. In: Proceedings of the International Conference on Programming Language Design and Implementation (PLDI). (2002)
16. Kathail, V., Schlansker, M., Rau, B.: Hpl-pd architectural specifications: Version 1.1. Technical Report Technical Report HPL-93-80(R.1), Hewlett-Packard Laboratories (Revised 2000)
17. Trimaran Consortium: TRIMARAN: An Infrastructure for Research in Instruction Level Parallelism. (http://www.trimaran.org)
18. Celoxica Inc.: Handel-C. (http://www.celoxica.com/tech/handel-c/)
19. Electronic Industries Alliance: Electronic Design Interface Format. (http://www.edif.org)