Laser-annealed junctions with advanced CMOS gate stacks for 32nm node: Perspectives on device performance and manufacturability

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2008, Pages 186-187

  Ortolland, C ^a   Noda, T ^a,c   Chiarella, T ^a   Kubicek, S ^a   Kerner, C ^a   Vandervorst, W ^a   Opdebeeck, A ^a   Vrancken, C ^a   Horiguchi, N ^a   De Potter, M ^a   Aoulaiche, M ^b   Rosseel, E ^a   Felch, S B ^d   Absil, P ^a   Schreutelkamp, R ^d   Biesemans, S ^a   Hoffmann, T ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c PANASONIC CORPORATION   (Japan)

^d APPLIED MATERIALS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; VLSI CIRCUITS;

DEVICE PERFORMANCE; IMPLANT OPTIMIZATION; JUNCTION LEAKAGES; LOW POWER APPLICATION; MANUFACTURABILITY; PERFORMANCE LOSS; PHYSICAL AND ELECTRICAL CHARACTERIZATIONS; STATE OF THE ART;

ANNEALING;

EID: 51949109916     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2008.4588612     Document Type: Conference Paper

References (13)

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