A one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2008, Pages 206-207

  Klim, Peter ^a   Barth, John ^a   Reohr, William ^b   Dick, David ^a   Fredeman, Gregory ^a   Koch, Gary ^a   Le, Hien ^a   Khargonekar, Aditya ^a   Wilcox, Pamela ^a   Golz, John ^a   Kuang, J B ^c   Mathews, Abraham ^a   Luong, Trong ^a   Ngo, Hung ^a   Freese, Ryan ^d   Hunter, Hillery ^b   Nelson, Erik ^a   Parries, Paul ^a   Kirihata, Toshiaki ^a   Iyer, Subramanian ^a  

^a IBM   (United States)

^b IBM RESEARCH   (United States)

^c IBM AUSTIN RESEARCH LABORATORY   (United States)

^d ADVANCED MICRO DEVICES   (United States)

Author keywords

eDRAM; SOI

Indexed keywords

BUILT-IN SELF TEST; CMOS INTEGRATED CIRCUITS; VLSI CIRCUITS;

CLOCK MULTIPLIERS; DATA RATES; EDRAM; EMBEDDED DRAM; ONE-TIME PROGRAMMABLES; SOI CMOS;

CHARGE PUMP CIRCUITS;

EID: 51949089957     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2008.4586008     Document Type: Conference Paper

References (7)

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