Stego-signature at logic synthesis level for digital design IP protection

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 4611-4614

  Cui, Aijiao ^a   Chang, Chip Hong ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CONSTRAINT THEORY; INFORMATION ANALYSIS; LOGIC DESIGN; TOPOLOGY;

IP DESIGNER INFORMATION; LOGIC RE-SYNTHESIS; MARKED CIRCUIT; SEED CELLS;

INTELLECTUAL PROPERTY;

EID: 34249810821     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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2. D. Kirovski and M. Potkonjak, "Local watermarks: methodology and application to behavioral synthesis," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Syst., vol. 22, no. 9, Sept. 2003, pp. 1277-1283.
3. D. Kirovski, Y. Y. Hwang, M. Potkonjak, and J. Cong, "Intellectual property protection by watermarking combinational logic synthesis solutions," in Proc. IEEE/ACM Int. Conf. on Computer-Aided Design, 8-12 Nov 1998, pp. 194-198.
4. E. Charbon, "Hierarchical watermarking in IC design," in Proc. IEEE Custom Integrated Circuits Conf., California, USA, May 1998, pp. 295-298.
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7. I. J. Cox, M. L. Miller, and J. A. Bloom, Digital Watermarking. Morgan Kaufmann Publishers, 2001.