A cyclic A/D conversion technique with improved SFDR

2007 International Symposium on Integrated Circuits, ISIC

Volumn , Issue , 2007, Pages 394-397

  Kuo, Chun Hsien ^a   Kuo, Tai Haur ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CALIBRATION; CAPACITORS; COMPARATORS (OPTICAL); DIGITAL ARITHMETIC; ELECTRIC EQUIPMENT; INTEGRATED CIRCUITS; MONTE CARLO METHODS; MOSFET DEVICES; MULTICARRIER MODULATION; SPECIFICATIONS;

CAPACITOR MISMATCHES; INTERNATIONAL SYMPOSIUM;

CAPACITANCE;

EID: 51549113803     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISICIR.2007.4441881     Document Type: Conference Paper

References (9)

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2. S.-Y. S. Chuang and T. L. Sculley, "A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter," IEEE J. Solid-State Circuits, vol. 37, pp. 674-683, June 2002.
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5. P. W. Li, M. J. Chin, P. R. Gray, and R. Castello, "A ratio independent algorithmic analog-to-digital conversion technique," IEEE J. Solid-State Circuits, vol. SC-19, pp. 1138-1143, Dec. 1984.
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7. P. C. Yu and H.-S. Lee, "A 2.5-V, 12-b, 5-MSample/s pipelined CMOS ADC," IEEE J. Solid-State Circuits, vol. 31, pp. 1854-1861, Dec. 1996.
8. P. C. Yu, S. Shehata, A. Joharapurkar, P. Chugh, A. R. Bugeja, Xiaohong Du, S.-U. Kwak, Y. Papantonopoulous, T. Kuyel, "A 14b 40MSample/s pipelined ADC with DFCA," International Solid-State Circuits Conference, pp. 136-137, Feb 2001.
9. S. H. Lewis and P. R. Gray, "A Pipelined 5 Msample/s 9-b analog-to-digital converter," IEEE J. Solid-State Circuits, vol. SC-22, pp. 954-961, Dec. 1987.