Efficient bit-level model reductions for automated hardware verification

Proceedings of the International Workshop on Temporal Representation and Reasoning

Volumn , Issue , 2008, Pages 164-172

  Tverdyshev, Sergey ^a   Alkassar, Eyad ^a  

^a SAARLAND UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

DOMAIN-SPECIFIC; INTERNATIONAL SYMPOSIUM; TRANSITION SYSTEMS;

ERROR ANALYSIS;

EID: 51549109385     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TIME.2008.11     Document Type: Conference Paper

References (29)

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