Verification of embedded memory systems using efficient memory modeling

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn II, Issue , 2005, Pages 1096-1101

  Ganai, Malay K ^a   Gupta, Aarti ^a   Ashar, Pranav ^a  

^a NEC LABORATORIES AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CONTROL THEORY; DATA STORAGE EQUIPMENT; FORMAL LOGIC; INTERFACES (COMPUTER); MATHEMATICAL MODELS;

BOUNDED MODEL CHECKING (BMC); CONTROL LOGIC; EMBEDDED MEMORY SYSTEMS; EMM CONSTRAINTS;

EMBEDDED SYSTEMS;

EID: 33646939006     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.325     Document Type: Conference Paper

References (21)

1. M. Pandey, R. Raimi, D. L. Beatty, and R. Brayton. "Formal Verification of PowerPC Arrays using Symbolic Trajectory Evaluation," Proceedings of DAC, 1996.
2. C. J. H. Seger and R. E. Bryant, "Formal Verification by Symbolic Evaluation by Partially-ordered Trajectories," Proceedings of Formal Method in System Design, 1995.
3. K. L. McMillan, Symbolic Model Checking: An Approach to the State Explosion Problem: Kluwer Academic Publishers, 1993.
4. E. M. Clarke, O. Grumberg, and D. Peled, Model Checking: MIT Press, 1999.
5. D. E. Long, "Model checking, abstraction and compositional verification," Carnegie Mellon University, 1993.
6. E. M. Clarke, O. Grumberg, S. Jha, Y. Lu, and H. Veith, "Counterexample-guided abstraction refinement," in Proceedings of CAV,vol. 1855, LNCS, 2000. pp. 154-169.
7. E. M. Clarke, A. Gupta, J. Kukula, and O. Strichman, "SAT based abstraction-refinement using ILP and machine learning techniques," in Proceedings of CAV, 2002.
8. P. Chauhan, E. M. Clarke, J. Kukula, S. Sapra. H. Veith, and D. Wang, "Automated Abstraction Refinement for Model Checking Large State Spaces using SAT based Conflict Analysis," in Proceedings of FMCAD, 2002.
9. K. McMillan and N. Amla, "Automatic Abstraction without Counterexamples," in Proceedings of TACAS, April 2003.
10. A. Gupta, M. Ganai, P. Ashar. and Z. Yang. "Iterative Abstraction using SAT-based BMC with Proof Analysis," in Proceedings of ICCAD. 2003.
11. J. R. Burch and D. L. Dill, "Automatic verification of pipelined microprocessor control," in Proceedings of CAV, 1994.
12. M. N. Velev, R. E. Bryant, and A. Jain, "Efficient Modeling of Memory Arrays in Symbolic Simulation," in Proceedings of CAV. 1997.
13. R. E. Bryant, S. German, and M. N. Velev, "Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Prepositional Logic," in Proceedings of CAV. 1999.
14. M. N. Velev, "Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors," in Proceedings of TA CAS, 2001.
15. R. E. Bryant, S. K. Lahiri, and S. A. Seshia, "Modeling and Verifying Systems using a Logic of Counter Arithmetic with Lambda Expressions and Uninterpreted Functions," in Proceedings of CAV, 2002.
16. A. Biere, A. Cimatti, E. M. Clarke, and Y. Zhu, "Symbolic Model Checking without BDDs," in Proceedings of TACAS, 1999.
17. M. Ganai, A. Gupta, and P. Ashar, "Distributed SAT and Distributed Bounded Model Checking," in Proceedings of CHARME, 2003.
18. M. Ganai, A. Gupta, and P. Ashar, "Efficient Modeling of Embedded Memories in Bounded Model Checking," in Proceedings of CAV, 2004.
19. M. Sheeran, S. Singh, and G. Stalmarck, "Checking Safety Properties using Induction and a SAT Solver," in Proceedings of FMCAD, 2000.
20. L. Zhang and S. Malik, "Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other Applications," in Proceedings of DATE, 2003.
21. M. Ganai, L. Zhang, P. Ashar, and A. Gupta, "Combining Strengths of Circuit-based and CNF-based Algorithms for a High Performance SAT Solver," in Proceedings of DAC, 2002.