On the verification of memory management mechanisms

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3725 LNCS, Issue , 2005, Pages 301-316

  Dalinger, Iakov ^a   Hillebrand, Mark ^a   Paul, Wolfgang ^a  

^a SAARLAND UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; COMPUTER SCIENCE; COMPUTER SIMULATION; FORMAL LOGIC; PROGRAM PROCESSORS; VIRTUAL REALITY;

MEMORY MANAGEMENT UNIT (MMU); PAGE FAULT HANDLER; USER COMPUTATION;

STORAGE ALLOCATION (COMPUTER);

EID: 33646404050     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11560548_23     Document Type: Conference Paper

References (20)

1. Boyer, R.S., ed.: Special issue on system verification. (JAR) 5 (1989)
2. Boyer, R.S., Moore, J S.: A Computational Logic Handbook. Academic Press (1988)
3. Hunt, W.A.: Microprocessor design verification. In JAR [1] 429-460
4. Moore, J S.: A mechanically verified language implementation. In JAR [1] 461-492
5. Young, W.D.: A mechanically verified code generator. In JAR [1] 493-518
6. Bevier, W.R.: Kit and the short stack. In JAR [1] 519-530
7. Moore, J S.: A grand challenge proposal for formal methods: A verified stack. In Aichernig, B.K., Maibaum, T.S.E., eds.: 10th Colloquium of UNU/IIST '02, Springer (2003) 161-172
8. The Verisoft Consortium: The Verisoft Project, http://www.verisoft.de/ (2003)
9. Gargano, M., Hillebrand, M., Leinenbach, D., Paul, W.: On the correctness of operating system kernels. In Kurd, J., Melham, T., eds.: TPHOLs '05. LNCS, Springer (2005)
10. Leinenbach, D., Paul, W., Petrova, E.: Towards the formal verification of a CO compiler: Code generation and implementation correctness. In Aichernig, B., Beckert, B., eds.: SEFM '05, IEEE Computer Society (2005)
11. Hillebrand, M., In der Rieden, T., Paul, W.: Dealing with I/O devices in the context of pervasive system verification. In: ICCD '05, IEEE Computer Society (2005) To appear.
12. Beyer, S., Jacobi, C., Kröning, D., Leinenbach, D., Paul, W.: Instantiating uninterpreted functional units and memory system: Functional verification of the VAMP. In Geist, D., Tronci, E., eds.: CHARME '03, Springer (2003) 51-65
13. Beyer, S.: Putting It All Together: Formal Verification of the VAMP. PhD thesis, Saarland University, Saarbrücken, Germany (2005)
14. Sawada, J., Hunt, W.A.: Processor verification with precise exceptions and speculative execution. In Hu, A.J., Vardi, M.Y., eds.: CAV '98, Springer (1998) 135-146
15. Müller, S.M., Paul, W.J.: Computer Architecture: Complexity and Correctness. Springer (2000)
16. Owre, S., Shankar, N., Rushby, J.M.: PVS: A prototype verification system. In Kapur, D., ed.: CADE '92, Springer (1992) 748-752
17. Aagaard, M., Ciubotariu, V., Higgins, J., Khalvati, F.: Combining equivalence verification and completion functions. In Hu, A., Martin, A., eds.: FMCAD '04, Springer (2004) 98-112
18. Paul, W., Dimova, D., Mancino, M.: Skript zur Vorlesung Systemarchitektur. http://www-wjp.cs.uni-sb.de/publikationen/Skript.pdf (2004)
19. Hillebrand, M.: Address Spaces and Virtual: Memory. Specification, Implementation, and Correctnesss. PhD thesis, Saarland University, Saarbrücken, Germany (2005)
20. Kröning, D.: Formal Verification of Pipelined Microprocessors. PhD thesis, Saarland University, Saarbrücken, Germany (2001)