Automatic memory reductions for RTL model verification

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2006, Pages 786-793

  Manolios, Panagiotis ^a   Srinivasan, Sudarshan K ^b   Vroon, Daron ^a  

^a Georgia Institute of Technology   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTING; DATA STORAGE EQUIPMENT; DESIGN;

COMPUTER-AIDED DESIGN; CURRENT STATE; EXPERIMENTAL RESULTS; FALSE POSITIVE (FP); GENERAL (CO); INTERNATIONAL CONFERENCES; MODEL VERIFICATION; RTL DESIGNS; TERM REWRITING;

MACHINE DESIGN;

EID: 46149105936     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320121     Document Type: Conference Paper

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