SRAM embedded memory with low cost, Flash EEPROM-switch-controlled redundancy

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2000, Pages 287-289

  McPartland, R J ^a   Loeper, D J ^a   Higgins, F P ^a   Singh, R ^b   MacDonald, G ^a   Komoriya, G ^a   Aymeloglu, S ^a   DePaolis, M V ^a   Leung, C W ^b  

^a LUCENT TECHNOLOGIES   (United States)

^b NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUILT-IN SELF TEST; CAPACITANCE; CAPACITORS; ELECTRIC BREAKDOWN; ELECTRIC CURRENTS; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC SWITCHES; EMBEDDED SYSTEMS; PROM; RANDOM ACCESS STORAGE;

CONTROL GATE CAPACITOR; FLASH CELL DESIGN; FOWLER-NORDHEIM TUNNEL ERASE GATE; JUNCTION BREAKDOWN VOLTAGE; STACKED RANDOM ACCESS STORAGE EMBEDDED MEMORY;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033683623     PISSN: 08865930     EISSN: None     Source Type: Journal    
DOI: 10.1109/CICC.2000.852668     Document Type: Article

References (1)

1. K. Ohsaki N. Asamoto S. Takagaki A Single Poly EEPROM Cell structure for use in standard CMOS processes IEEE J. Solid State Circuits 29 311 316 March 1994